Philips Semiconductors

SC16C550B

5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs

Product data

Rev. 02 — 14 December 2004

13 of 47

9397 750 14446

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

6.4 Hardware/software and time-out interrupts

Following a reset, the transmitter interrupt is enabled, the SC16C550B will issue an

interrupt to indicate that the Transmit Holding Register is empty. This interrupt must

be serviced prior to continuing operations. The ISR register provides the current

singular highest priority interrupt only. Only after servicing the higher pending

interrupt will the lower priority be reflected in the status register. Servicing the

interrupt without investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same

interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the

number of characters have reached the programmed trigger level. In this case, the

SC16C550B FIFO may hold more characters than the programmed trigger level.

Following the removal of a data byte, the user should re-check LSR[0] for additional

characters. A Receive Time Out will not occur if the receive FIFO is empty. The

time-out counter is reset at the center of each stop bit received or each time the

receive holding register (RHR) is read. The actual time-out value is 4 character time,

including data information length, start bit, parity bit, and the size of stop bit, i.e., 1

×,

1.5

×, or 2× bit times.

(1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing

the sixteenth byte.

(2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is

more than one byte of space available.

(3) When the receive FIFO is full, the first receive buffer register read re-asserts RTS.

Fig 8.

RTS functional timing waveforms, RCV FIFO trigger level = 14 bytes.

byte 14

byte 15

RX

RTS

IOR

(RD RBR)

Start

byte 18

Stop

Start

byte 16

Stop

002aaa051

RTS released after the

first data bit of byte 16