PC755CMZFU366LE datasheet(8/50 Pages) ATMEL

8 / 50 page

PC755/745

2138D–HIREL–06/03

Pinout Listings

Table 1 provides the pinout listing for the PC745, 255 PBGA package.

Table 1. Pinout Listing for the PC745, 255 PBGA Package

Signal Name

Pin Number

Active

I/O

I/F Voltages Supported(1)

1.8V/2.0V

3.3V

A[0

-31]

C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2,

E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13,

K1, G15, K2, H16, M1, J15, P1

High

I/O

–

AACK

Low

Input

–

ABB

Low

I/O

–

AP[0

-3]

C1, B4, B3, B2

High

I/O

–

ARTRY

Low

I/O

–

AVDD

A10

–

Low

Input

–

Low

Output

–

BVSEL(3)(4)(5)

High

Input

GND

3.3V

Low

Output

–

CKSTP_IN

Low

Input

–

CKSTP_OUT

Low

Output

–

CLK_OUT

–

Output

–

DBB

J14

Low

I/O

–

DBG

Low

Input

–

DBDIS

H15

Low

Input

–

DBWO

Low

Input

–

DH[0

-31]

P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11,

R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6,

N6, R6, T6, R5, N5, T5, T4

High

I/O

–

DL[0

-31]

K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16,

N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12,

T13, P3, N3, N4, R3, T1, T2, P4, T3, R4

High

I/O

–

DP[0

-7]

M2, L3, N2, L4, R1, P2, M4, R2

High

I/O

–

DRTRY

G16

Low

Input

–

GBL

Low

I/O

–

GND

C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6,

G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8,

K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5,

P12

HRESET

Low

Input

–

INT

B15

Low

Input

–

L1_TSTCLK(2)

D11

High

Input

–

L2_TSTCLK(2)

D12

High

Input

–

LSSD_MODE(2)

B10

Low

Input

–

-–

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