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HT68F001

Cost-Effective Flash MCU

HT68F001

Cost-Effective Flash MCU

Table of Contents

Features............................................................................................................ 5

CPU Featu�es ......................................................................................................................... 5

Pe�iphe�al Featu�es................................................................................................................. 5

General Description......................................................................................... 5

Block Diagram.................................................................................................. 6

Pin Assignment................................................................................................ 6

Pin Description ................................................................................................ 7

Absolute Maximum Ratings............................................................................ 7

D.C. Characteristics......................................................................................... 8

�pe�ating Voltage Cha�a�te�isti�s........................................................................................... 8

�pe�ating Cu��ent Cha�a�te�isti�s........................................................................................... 8

Stand�y Cu��ent Cha�a�te�isti�s ............................................................................................. 8

A.C. Characteristics......................................................................................... 9

Low Speed Inte�nal �s�illato� Cha�a�te�isti�s – LIRC – F�equen�y A��u�a�y........................ 9

System Sta�t Up Time Cha�a�te�isti�s .................................................................................... 9

Input/Output Characteristics ........................................................................ 10

Power on Reset Characteristics................................................................... 10

System Architecture.......................................................................................11

Clo�king and Pipelining..........................................................................................................11

P�og�am Counte�................................................................................................................... 1�

Sta�k ..................................................................................................................................... 1�

A�ithmeti� and Logi� Unit – ALU ........................................................................................... 13

Flash Program Memory................................................................................. 14

St�u�tu�e................................................................................................................................ 14

Spe�ial Ve�to�s ..................................................................................................................... 14

Look-up Ta�le........................................................................................................................ 14

Ta�le P�og�am Example........................................................................................................ 15

In Ci��uit P�og�amming – ICP ............................................................................................... 15

�n-Chip De�ug Suppo�t – �CDS ......................................................................................... 16

Data Memory .................................................................................................. 17

St�u�tu�e................................................................................................................................ 1�

Gene�al Pu�pose Data Memo�y ............................................................................................ 1�

Spe�ial Pu�pose Data Memo�y ............................................................................................. 18

Special Function Register Description........................................................ 19

Indi�e�t Add�essing Registe�s – IAR0 ................................................................................... 19

Memo�y Pointe�s – MP0........................................................................................................ 19

A��umulato� – ACC............................................................................................................... �0

P�og�am Counte� Low Registe� – PCL.................................................................................. �0

Look-up Ta�le Registe�s – TBLP........................................................................................... �0

Status Registe� – STATUS.................................................................................................... �0