© VITESSE SEMICONDUCTOR CORPORATION

Page 13

3/4/99

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Datasheet

VSC7126

1.0625 Gbits/sec Fibre

Channel Transceiver

G52148-0, Rev. 4.3

65,63,59,57,

55,52,50,48,

45,43,64,62,

58,56,54,51,

49,47,44,42

R0:19

Receive Data Bus, Bits 0 thru 19

OUTPUTS - TTL

20-bit received character. Parallel data on this bus is clocked out on the rising edge of

RBC(0). R0 is the first bit received on RX+/RX-.

34

EWRAP

Enable Internal WRAP Mode.

INPUT - TTL

LOW for Normal Operation. When HIGH, an internal loopback path from the

transmitter to the receiver is enabled, TX+ = HIGH and TX- is LOW.

70

69

RX+

RX-

Receive Serial Inputs

INPUTS - Differential PECL

The receiver inputs when EWRAP is LOW. Internally biased to VDD/2, with 3.3K

Ω

resistors to VDD and GND.

(AC Coupling recommended)

39

38

RBC(0)

RBC(1)

Recovered Byte Clock and Complement

OUTPUT - TTL

Recovered clock and complement derived from one twentieth of the RX+/- data stream.

The rising edge of RBC(0) corresponds to a new word on R0:19.

27

EN_CDET

ENable Comma DETect.

INPUT - TTL

Enables comma detection and word resynchronization when HIGH. When LOW, keeps

current word alignment and disables comma detection.

37

COMDET

COMma DETect

OUTPUT - TTL

This output goes HIGH to indicate that R0:6 contains a Comma Character (‘0011111’).

COMDET will go HIGH only during a cycle when RBC(0) is falling. COMDET is

enabled by EN_CDET being HIGH.

35

TXEN#

Transmitter ENable

INPUT - TTL

When LOW, the TX outputs transmit serial data. When HIGH, the TX+ is HIGH and the

TX- is LOW.

66

LUNUSE

Link UNUSE

OUTPUT - TTL

Normally is LOW. If R0:19 is all LOW or all HIGH and EWRAP is LOW, this output

will be asserted HIGH to indicate an open link on RX+/-.

26

28

29

TEST1

TEST2

TEST3

TEST Mode Pins

INPUT - TTL

Factory test pins. Tie to VDD for normal operation.

1,21,30,68,72

VSS

Digital Ground

40,41,60,61

VSST

Digital Ground for TTL Outputs

74

VSSA

Analog Ground

7,13,25,32,33,

67,71,75

VDD

Digital Power (3.3V)

36,46,53

VDDT

Digital Power for TTL outputs (3.3V)

76,80

VDDP

Digital Power for PECL outputs (3.3V)

73

VDDA

Analog Power (3.3V)

78

N/C

Not Internally Connected.

Pin #

Name

Description