SSD1852Z datasheet(13/55 Pages) ETC

13 / 55 page

SSD1852

Rev 1.0

01/2003

SOLOMON

PIN DESCRIPTION

6.1

RES

This pin is reset signal input. When the pin is low, initialization of the chip is executed.

6.2

PS0 & PS1

These two pins determine the interface protocol between the driver and MCU. Refer to the

following table.

PS0

PS1

Interface

3-wire SPI (write only)

4-wire SPI (write only)

8080 parallel interface (read and write allowed)

6800 parallel interface (read and write allowed)

6.3

This pin is chip select input. The chip is enabled for display data/command transfer only when

is low.

6.4

D/ C

This input pin is to identify display data/command cycle. When the pin is high, the data written to

the driver will be written into display RAM. When the pin is low, the data will be interpreted as

command. This pin must be connected to VSS when 3-lines SPI interface is used.

6.5

R/W ( WR )

This pin is a microprocessor interface signal. When interfacing 6800-series microprocessor, the

signal indicates read mode when high and write mode when low. When interfacing 8080-

microprocessor, the data write operation is initiated when R/W( WR ) is low and the chip is

selected.

6.6

E( RD )

This pin is microprocessor interface signal. When interfacing 6800-series microprocessor, the

data operation is initiated when E( RD ) is high and the chip is selected. When interfacing 8080-

microprocessor, the data read operation is initiated when E( RD ) is low and the chip is selected.

6.7

D0~D7

These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus.

When serial mode is selected, D7 is the serial data input SDA and D6 is the serial clock input

SCK.

6.8

INTRS

This pin is an input pin to enable the internal resistors network for the voltage regulator when

INTRS is high. When external regulator is used, this pin must be connected to VSS, and external

resistors R2/R1 should be connected to VL6, VR and VSS.

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