DA9063L datasheet(68/173 Pages) DIALOG

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DA9063L

System PMIC for Mobile and Automotive Applications

Datasheet

DA9063L_2v1

05-Apr-2017

CFR0011-120-00

68 of 173

Events on GPI10 can be used to control the progress of the power sequencer. Processing ID

WAIT_STEP causes the sequencer to wait until GPI10 changes into its active state.

Note

Supplies directly enabled/disabled from GPI1, 2, or 13 have to be excluded from the power sequencer control

(IDs of these supplies should point into a slot higher than MAX_COUNT)

If defined as an output, GPO0, 1, 3 to 6, 10 to 11, and 13 to 15 can be configured to be open-drain

instead of push-pull. The supply rail can be individually selected from either VDD_IO1 or VDD_IO2.

By disabling the internal 120

kΩ pull-up resistor when in open-drain mode, the GPO can also be

supplied from an external rail (see registers CONFIG_K and CONFIG_L). The GPO output state

reflects the respective register bit GPIOx_MODE.

When configured as outputs, GPO 2, 7, 8, 9, and 11 can be controlled by the DA9063L power

sequencer. Five pairs of level asserting and level releasing IDs (GP_RISE1_STEP/

GP_FALL1_STEP to GP_RISE5_STEP/GP_FALL5_STEP) may be assigned individually to slots of

the power sequencer, which trigger the configured level transition on the GPOs when processing the

related ID during powering up (see Table 31 for assignments). The configured level change is

inverted when processing the IDs during powering down. These are intended for use as enable

signals either for external regulators or other devices in the system.

When the GPIO unit is off (POR), all ports are configured as open drain output with high level (pass

device switched off, high impedance state). When leaving POR, the pull-up or pull-down resistors are

configured from registers CONFIG_K and CONFIG_L. When the GPIO unit is temporarily disabled by

the power sequencer (via GPI_DIS or PMCONT_DIS) level transitions on inputs are no longer

detected and I/O drivers keep their configuration and programmed levels.

GPO12 can be driven by the state of VDD_MON to provide an active high ‘Power good’ signal

(selected via GPIO12_PIN).

GPO10, 11, 14, and 15 are extended power GPO ports, where the maximum sink current is 11 mA

and the maximum source current is 4 mA. This enables driving LEDs. The output ports GPO11,

GPO14, and GPO15 can be toggled with a configurable periodic pulse configured via BLINK_FRQ

and BLINK_DUR and include an optional PWM control. The generated PWM signals have a duty

cycle from 0 % to 100 % with a repetition frequency of 21 kHz and 95 steps (using one 2 MHz clock

for each step). The duty cycle is set by the controls GPO11_PWM, GPO14_PWM, and

GPO15_PWM, with any value larger than 0 enabling the PWM mode of operation. The PWM control

can also be made to dim the brightness between its current value and a new value at a rate of 32 ms

per step. Selection of this mode is set by GPO11_DIM, GPO14_DIM, and GPO15_DIM. When set to

zero the PWM ratio immediately changes. This creates a common anode tricolor LED brightness

control. Flashing is driven from the crystal oscillator when control CRYSTAL has been asserted;

otherwise an auxiliary on-chip oscillator is used.

LEDs are recommended to be low-side driven (using the GPIOs in sink mode) which is configured by

setting GPIOx_MODE = 1.

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