AD9670BBCZ datasheet(9/53 Pages) AD

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AD9670

Data Sheet

Rev. A | Page 8 of 52

SWITCHING SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, full temperature range (0°C to 85°C), RF decimator bypassed, digital

demodulator and baseband decimator bypassed, unless otherwise noted.

Table 3.

Parameter1

Temperature

Min

Typ

Max

Unit

CLOCK2

Clock Rate

40 MSPS (Mode I)

Full

20.5

MHz

65 MSPS (Mode II)

Full

20.5

MHz

80 MSPS (Mode III)3

Full

20.5

MHz

125 MSPS (Mode IV)4

Full

20.5

125

MHz

Clock Pulse Width High (tEH)

Full

3.75

Clock Pulse Width Low (tEL)

Full

3.75

OUTPUT PARAMETERS2, 5

Propagation Delay (tPD)

Full

10.8 − 1.5 × tDCO

10.8

10.8 + 1.5 × tDCO

Rise Time (tR) (20% to 80%)

Full

300

Fall Time (tF) (20% to 80%)

Full

300

DCO Period (tDCO)6

Full

tSAMPLE/7

FCO Propagation Delay (tFCO)

Full

10.8 − 1.5 × tDCO

10.8

10.8 + 1.5 × tDCO

DCO Propagation Delay (tCPD)7

Full

tFCO + (tSAMPLE/28)

DCO to Data Delay (tDATA)7

Full

(tSAMPLE/28) − 300

(tSAMPLE/28)

(tSAMPLE/28) + 300

DCO to FCO Delay (tFRAME)7

Full

(tSAMPLE/28) − 300

(tSAMPLE/28)

(tSAMPLE/28) + 300

Data-to-Data Skew (tDATA-MAX − tDATA-MIN)

Full

±225

±400

TX_TRIG to CLK Setup Time (tSETUP)

25°C

TX_TRIG to CLK Hold Time (tHOLD)

25°C

Wake-Up Time

Standby

25°C

μs

Power-Down

25°C

375

μs

ADC Pipeline Latency

Full

Clock cycles

APERTURE

Aperture Uncertainty (Jitter)

25°C

ps rms

LO GENERATION

MLO8 Frequency

4LO Mode

Full

MHz

8LO Mode

Full

MHz

16LO Mode

Full

160

MHz

RESET9 to MLO Setup Time (tSETUP)

Full

tMLO10/2

RESET to MLO Hold Time (tHOLD)

Full

tMLO10/2

1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and

Evaluation.

2 The clock can be adjusted via the SPI.

3 Mode III must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS.

4 Mode IV must have the RF decimator enabled because the maximum data rate of the baseband demodulator and decimator is 65 MSPS.

5 Measurements were taken using a device soldered to FR-4 material.

6 In the typical value, tSAMPLE/7, 7 is based on the number of bits (14) divided by 2 because the interface uses double data rate (DDR) sampling.

7 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles.

8 MLO refers to the differential signal created via the MLO− pin and the MLO+ pin. This notation is used throughout the data sheet.

9 RESET refers to the differential signal created via the RESET− pin and the RESET+ pin. This notation is used throughout the data sheet.

10 The period of the MLO clock signal is represented by tMLO.

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