AD9278

Data Sheet

Rev. A | Page 6 of 44

DIGITAL SPECIFICATIONS

AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.

Table 2.

Parameter1

Temperature

Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage2

Full

250

mV p-p

Input Common-Mode Voltage

Full

1.2

V

Input Resistance (Differential)

25°C

20

kΩ

Input Capacitance

25°C

1.5

pF

CW 4LO INPUTS (4LO+, 4LO−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage2

Full

250

mV p-p

Input Common-Mode Voltage

Full

1.2

V

Input Resistance (Differential)

25°C

20

kΩ

Input Capacitance

25°C

1.5

pF

LOGIC INPUTS (PDWN, STBY, SCLK, RESET)

Logic 1 Voltage

Full

1.2

3.6

V

Logic 0 Voltage

Full

0.3

V

Input Resistance

25°C

30

kΩ

Input Capacitance

25°C

0.5

pF

LOGIC INPUT (CSB)

Logic 1 Voltage

Full

1.2

3.6

V

Logic 0 Voltage

Full

0.3

V

Input Resistance

25°C

70

kΩ

Input Capacitance

25°C

0.5

pF

LOGIC OUTPUT (SDIO)3

Full

1.2

DRVDD + 0.3

V

Full

0

0.3

V

Input Resistance

25°C

30

Input Capacitance

25°C

2

DIGITAL OUTPUTS (DOUTx+, DOUTx−), (ANSI-644)

Logic Compliance

LVDS

Full

247

454

mV

Full

1.125

1.375

V

Output Coding (Default)

Offset binary

DIGITAL OUTPUTS (DOUTx+, DOUTx−),

(LOW POWER, REDUCED SIGNAL OPTION)

Logic Compliance

LVDS

Full

150

250

mV

Full

1.10

1.30

V

Output Coding (Default)

Offset binary

LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)

Full

0.05

V

1

See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were

completed.

2

Specified for LVDS and LVPECL only.

3

Specified for 13 SDIO pins sharing the same connection.