LTC5100EUF datasheet(2/52 Pages) LINER

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LTC5100

sn5100 5100fs

VDD, VDD(HS) ............................................................. 4V

IN+, IN– (Cml_en = 1) (Note 6)

Peak Voltage ........... VDD(HS) – 1.2V to VDD(HS) + 0.3V

Average Voltage...... VDD(HS) – 0.6V to VDD(HS) + 0.3V

IN+, IN– (Cml_en = 0) (Note 4) .. –0.3V to VDD(HS) + 0.3V

Cml_en = 0 (Note 4)

Peak Difference Between IN+ and IN– ..............

±2.5V

Average Difference Between IN+ and IN– .......

±1.25V

MODA, MODB (Transmitter Disabled) .... –0.3V to 2.75V

MODA, MODB

(Transmitter Enabled) ............ VDD(HS) – 2.75V to 2.75V

EN, SDA, SCL, FAULT ..................... –0.3V to VDD + 0.3V

MD, SRC ................................................... –0.3V to VDD

Ambient Operating Temperature Range .. – 40

°C to 85°C

Storage Temperature Range ................ – 65

°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

ABSOLUTE

AXI U

RATI GS

PACKAGE/ORDER I FOR ATIO

(Note 1)

ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C; VDD = VDD(HS) = 3.3V, IS = 24mA; IM = 12mA (IMPP = 24mA); 49.9Ω, 1%

resistor from SRC (Pin 14) to MODA (Pin 11); 50

Ω, 1% load AC coupled to MODB (Pin 10); 10nF, 10% capacitor from SRC (Pin 14) to

VSS; Cml_en = 0, Lpc_en = 1, transmitter enabled, unless otherwise noted. Test circuit in Figure 5.

ORDER PART

NUMBER

UF PART MARKING

5100

LTC5100EUF

TJMAX = 125°C, θJA = 37°C/W

EXPOSED PAD IS VSS (PIN 17)

MUST BE SOLDERED TO PCB GROUND PLANE

16 15 14 13

TOP VIEW

UF PACKAGE

16-LEAD (4mm

× 4mm) PLASTIC QFN

VSS

IN+

IN –

VSS

MODA

MODB

VSS

1/16 of Full-Scale IS Current

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Power Supply

VDD, VDD(HS) Operating Voltage

3.135

3.3

3.465

VDD + VDD(HS) Quiescent Current,

VDD = 3.465V

Excluding the SRC Pin Current (Note 2)

Transmitter Disabled, Power_down_en = 1

4.5

Transmitter Enabled, Is_rng = Im_rng = 3

Impp = 24mA

High Speed Data Inputs (IN+ and IN– Pins) (Test Circuit, Figure 5)

Input Signal Amplitude

Peak-to-Peak Differential Voltage (The Single-

500 to 2400

mVP-P

Ended Peak-to-Peak Voltage is One Half the

Differential Voltage)

Common Mode Input Signal Range (Note 3)

Cml_en = 0 (Note 4)

VDD(HS)

Differential Input Resistance

80 to 120

Ω

Common Mode Input Resistance

Cml_en = 0 (Note 5)

Ω

Open-Circuit Voltage

Cml_en = 0 (Note 5)

1.65

SRC Pin Current, IS

Full-Scale IS Current

Is_rng = 0

Is_rng = 1

Is_rng = 2

Is_rng = 3

Minimum Operating Current (Note 7)

Resolution

Bits

SRC Pin Voltage Range

1.2

VDD –V

200mV

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