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LTC1840IGN bảng dữ liệu(PDF) 3 Page - Linear Technology

tên linh kiện LTC1840IGN
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LTC1840IGN bảng dữ liệu(HTML) 3 Page - Linear Technology

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LTC1840
3
1840f
ELECTRICAL CHARACTERISTICS The q denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 3V
Note 1: Absolute Maximum Ratings are those values beyond
which the life of a device may be impaired.
Note 2: Guaranteed by design not subject to test.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital Inputs SCL, SDA
VIH
Digital Input High Voltage
q
1.4
V
VIL
Digital Input Low Voltage
q
0.6
V
VLTH
Logic Threshold Voltage
(Note 2)
1
V
ILEAK
Digital Input Leakage
VCC = 5V and 0V, VIN = GND to VCC
±1
µA
CIN
Digital Input Capacitance
(Note 2)
10
pF
Digital Output SDA
VOL
Digital Output Low Voltage
IPULL-UP = 3mA
q
0.4
V
Digital Output FAULT
VOL
Digital Output Low Voltage
IPULL-UP = 1mA
q
0.4
V
Digital Inputs TACHA, TACHB
VIH
Digital Input High Voltage
q
0.7VCC
V
VIL
Digital Input Low Voltage
q
0.3VCC
V
ILEAK
Digital Input Leakage
VCC = 5V and 0V, VIN = GND to VCC
±1
µA
Digital Input BLAST
VLTH
Logic Threshold Voltage
Measured on BLAST Falling Edge
0.95
1.0
1.05
V
VIHYST
Input Hysteresis
(Note 2), Measured on Rising Edge
20
mV
ILEAK
Digital Input Leakage
VCC = 5V and 0V, VIN = GND to VCC
±1
µA
Address Inputs A0, A1
VIH
Input High Voltage
q
0.9VCC
V
VIL
Input Low Voltage
q
0.1VCC
V
IIN
Input Current
AX Shorted to GND or VCC, VCC = 5V
±100
µA
Timing Characteristics
fI2C
I2C Operating Frequency
(Note 2)
0
100
kHz
tBUF
Bus Free Time Between
(Note 2)
4.7
µs
Stop and Start Condition
thD, STA
Hold Time after (Repeated)
(Note 2)
4
µs
Start Condition
tsu, STA
Repeated Start Condition
(Note 2)
4.7
µs
Setup Time
tsu, STO
Stop Condition Setup Time
(Note 2)
4
µs
thD, DAT
Data Hold Time
300
ns
tsu, DAT
Data Setup Time
(Note 2)
250
ns
tLOW
Clock Low Period
(Note 2)
4.7
µs
tHIGH
Clock High Period
(Note 2)
4.0
µs
tf
Clock, Data Fall Time
(Note 2)
300
ns
tr
Clock, Data Rise Time
(Note 2)
1000
ns



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