PCI7510 datasheet(67/234 Pages) TI

67 / 234 page

3–27

For the operating system (OS) to manage the device power states on the PCI bus, the PCI function must support four

power-management operations. These operations are:

•

Capabilities reporting

•

Power status reporting

•

Setting the power state

•

System wake-up

The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of

capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI

offset 06h, see Section 4.6).

The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI7510 device, a

CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h.

The first byte of each capability register block is required to be a unique ID of that capability. PCI power management

has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there

are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer

are specific to the capability of the function. The PCI power-management capability implements the register block

outlined in Table 3–17.

Table 3–17. Power-Management Registers

OFFSET

Power-management capabilities

Next item pointer

Capability ID

A0h

Data

Power-management control/status register bridge support extensions

Power-management control/status (CSR)

A4h

The power-management capabilities register (PCI offset A2h, see Section 4.43) is a static read-only register that

provides information on the capabilities of the function related to power management. The power-management

control/status register (PCI offset A4h, see Section 4.44) enables control of power-management states and

enables/monitors power-management events. The data register is an optional register that can provide dynamic data.

For more information on PCI power management, see the PCI Bus Power Management Interface Specification for

PCI to CardBus Bridges.

3.9.9.1 Function 2 Power Management

The PCI7510 device complies with the PCI Bus Power Management Interface Specification. The device supports the

D0 (unitialized), D0 (active), D1, D2, and D3 power states as defined by the power management definition in the 1394

Open Host Controller Interface Specification, Appendix A4.

Table 3–18. Function 2 Power-Management Registers

OFFSET

Power-management capabilities

Next item pointer

Capability ID

44h

Data

Power-management control/status register bridge support extensions

Power-management control/status (CSR)

48h

3.9.9.2 Function 3 Power Management

The PCI Bus Power Management Interface Specification is applicable for the firmware loader. This function supports

the D0 and D3 power states.

Table 3–19. Function 3 Power-Management Registers

OFFSET

Power-management capabilities

Next item pointer

Capability ID

44h

Data

Power-management control/status register bridge support extensions

Power-management control/status (CSR)

48h

3.9.10 CardBus Bridge Power Management

The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in

December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power

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