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6.2
I2C Transmission to ATECC508A
The transmission of data from the system to the ATECC508A is summarized in the table below. The order
of transmission is as follows:
•
Start Condition
•
Device Address Byte
•
Word Address Byte
•
Optional Data Bytes (1 through N)
•
Stop Condition
Figure 6-4. Normal I2C Transmission to ATECC508A
1-7
8
9
1-7
8
9
1-7
8
9
1-7
8
9
1-7
8
9
SCL
SDA
S
P
R/W
ACK1
ACK1
ACK1
Word
Address
Data 1
ACK1
Data 2
Start
Condition
Stop
Condition
Device
Address
ACK1
Data N
SDA is driven low by ATECC508A ACK periods.
The tables below label the bytes of the I/O transaction. The column labeled “I2C Name” provides the
name of the byte as described in the AT24C16 data sheet.
Table 6-1. I2C Transmission to ATECC508A
Name
I2C Name
Description
Device
Address
Device
Address
This byte selects a particular device on the I2C interface. ATECC508A is selected if
the data shifted out on clock pulses 1-7 match the data stored in the I2C_Address
byte in the Configuration zone. Data is shifted out MSb first. Bit 0 of this byte (clock
pulse 8) is the standard I2C R/W bit, and should be zero to indicate a write operation
(the bytes following the device address travel from the master to the slave).
Word Address Word
Address
This byte should have a value of 0x03 for normal operation. See Sections Word
Address Values and Address Counter for more information.
Command
Data1,N
The command group, consisting of the count, command packet, and the two byte
CRC. The CRC is calculated over the size and packet bytes. See Section I/O
Groups.
Because the device treats the command input buffer as a FIFO, the input group can be sent to the device
in one or many I2C command groups. The first byte sent to the device is the count, so after the device
receives that number of bytes, it will ignore any subsequently received bytes until execution is finished.
The system must send a Stop condition after the last command byte to ensure that ATECC508A will start
the computation of the command. Failure to send a Stop condition may eventually result in a loss of
synchronization; see Section I2C Synchronization for recovery procedures.
6.2.1
Word Address Values
During an I2C write packet, the ATECC508A interprets the second byte sent as the word address, which
indicates the packet function as it is described in the table below:
ATECC508A
I2C Interface
© 2017 Microchip Technology Inc.
Datasheet Complete
DS20005927A-page 42



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