DSP56166ROM datasheet(35/63 Pages) MOTOROLA

35 / 63 page

PRELIMINARY - 6/15/93

DSP56166 Technical Data Sheet

MOTOROLA

AC Electrical Characteristics

External Bus Asynchronous Timing

VCC = 5.0 Vdc +/- 10%, TJ = -40 to +125˚ C, CL = 50 pF + 1 TTL Load.

cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles

WS = Number of Wait States, Determined by BCR Register (WS = 0 to 31)

WT = WS*cyc=2T*WS

Num

Characteristic

60MHz

Unit

Min

Max

WR and RD Deassertion High to BS

Assertion Low (2 Successive Bus Cycles)

TBD

Address Valid to WR Assertion

TBD

WR Width Assertion

WS=0

WS>0

TBD

—

WR Deassertion to R/W, Address Invalid

TBD

—

WR Assertion to D0-D15 Out Valid

TBD

Data Out Hold Time from WR Deassertion

TBD

Data Out Set up Time to WR

WS=0

Deassertion

WS>0

TBD

—

RD Deassertion to Adress not valid

TBD

—

Address valid to RD Deassertion

TBD

—

Input data hold to RD Deassertion

TBD

—

RD Assertion width

WS=0

WS>0

TBD

—

Address valid to input data valid WS=0

WS>0

—

TBD

Address valid to RD Assertion

TBD

RD Assertion to input data valid WS=0

WS>0

—

TBD

WR Deassertion to RD Assertion

TBD

—

RD Deassertion to RD Assertion

TBD

—

WR Deassertion to WR Assertion

TBD

—

RD Deassertion toWR Assertion

TBD

—

DSP56166ROM bảng dữ liệu(PDF) 35 Page - Motorola, Inc

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