CY29773
Document #: 38-07573 Rev. **
Page 2 of 12
Pin Description [1]
Pin
Name
I/O
Type
Description
11
PECL_CLK
I, PU
LVPECL
LVPECL reference clock input.
12
PECL_CLK#
I
LVPECL
LVPECL reference clock input.
9
TCLK0
I, PU
LVCMOS LVCMOS/LVTTL reference clock input.
10
TCLK1
I, PU
LVCMOS LVCMOS/LVTTL reference clock input.
44,46,48,50
QA(3:0)
O
LVCMOS Clock output bank A.
32,34,36,38
QB(3:0)
O
LVCMOS Clock output bank B.
16,18,21,23
QC(3:0)
O
LVCMOS Clock output bank C.
29
FB_OUT
O
LVCMOS Feedback clock output. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This
input should be at the same voltage rail as input reference clock. See
Table 1. Frequency Table.
25
SYNC
O
LVCMOS Synchronous pulse output. This output is used for system synchro-
nization.
6
PLL_EN
I, PU
LVCMOS PLL enable/bypass input. When Low, PLL is disabled/bypassed and
the input clock connects to the output dividers.
2
MR#/OE
I, PU
LVCMOS Master reset and Output enable/disable input. See Table 2.
Function Table (Configuration Controls).
8
TCLK_SEL
I, PU
LVCMOS LVCMOS Clock reference select input. See Table 2. Function Table
(Configuration Controls).
7
REF_SEL
I, PU
LVCMOS LVCMOS/LVPECL Reference select input. See Table 2. Function
Table (Configuration Controls).
52
VCO_SEL
I, PU
LVCMOS VCO Operating frequency select input. See Table 2. Function Table
(Configuration Controls).
14
INV_CLK
I, PU
LVCMOS QC(2,3) Phase selection input. See Table 2. Function Table (Config-
uration Controls).
5,26,27
FB_SEL(2:0)
I, PU
LVCMOS Feedback divider select input. See Table 6.
42,43
SELA(1,0)
I, PU
LVCMOS Frequency select input, Bank A. See Table 3. Function Table (Bank
A).
40,41
SELB(1,0)
I, PU
LVCMOS Frequency select input, Bank B. See Table 4. Function Table (Bank
B).
19,20
SELC(1,0)
I, PU
LVCMOS Frequency select input, Bank C. See Table 5. Function Table (Bank
C).
3
SCLK
I, PU
LVCMOS Serial clock input.
4
SDATA
I, PU
LVCMOS Serial data input.
45,49
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks.[2,3]
33,37
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks.[2,3]
22,17
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks.[2,3]
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL.[2,3]
28
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs.[2,3]
1
AVSS
Supply
Ground
Analog Ground.
15,24,30,35,39,47,51 VSS
Supply
Ground
Common Ground.
Notes:
1.
PU = Internal pull up, PD = Internal pull down.
2.
A 0.1-
µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.
AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins.
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