CS5460A datasheet(49/54 Pages) CIRRUS

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CS5460A

allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.

Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command.

Can be deactivated only by sending a port initialization sequence to the serial port (or by exe-

cuting a software/hardware reset). When writing to the Status Register, this bit is ignored.

LSD

Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-

old (PMLO), with respect to VA- pin. For a given part, PMLO can be as low as 2.3 V. LSD bit

cannot be permanently reset until the voltage at PFMON pin rises back above the high-voltage

threshold (PMHI), which is typically 100mV above the device’s low-voltage threshold. PMHI will

never be greater than 2.7 V.

IOD

Modulator oscillation detect on the current channel. Set when the modulator oscillates due to

an input above Full Scale. Note that the level at which the modulator oscillates is significantly

higher than the current channel’s Differential Input Voltage Range.

VOD

Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to

an input above Full Scale. Note that the level at which the modulator oscillates is significantly

higher than the current channel’s Differential Input Voltage Range.

Note:

The IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the

power line. This event should not be confused with a DC overload situation at the

inputs, when the IOD and VOD bits will re-assert themselves even after being

cleared, multiple times.

WDT

Watch-Dog Timer. Set when there has been no reading of the Energy Register for more than

5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy Register, then

write to the Status Register with this bit set to logic '1'. When MCLK/K is not 4.096 MHz, the

time duration is 5 * [4.096 MHz / (MCLK/K)] seconds.

ID3:0

Revision/Version Identification.

EOOR

The internal EOUT Energy Accumulation Register went out of range. Note that the EOUT En-

ergy Accumulation Register is different than the Energy Register available through the serial

port. This register cannot be read by the user. Assertion of this bit can be caused by having

an output rate that is too small for the power being measured. The problem can be corrected

by specifying a higher frequency in the Pulse-Rate Register.

EOR

Energy Out of Range. Set when the Energy Register overflows, because the amount of energy

that has been accumulated during the pending computation cycle is greater than the register’s

highest allowable positive value or below the register’s lowest allowable negative value.

VROR

RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the

RMS Voltage Register.

IROR

RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the

RMS Current Register.

PWOR

Power Calculation Out of Range. Set when the

magnitude of the calculated power is too large

to fit in the Instantaneous Power Register.

VOR

Voltage Out of Range.

IOR

Current Out of Range. Set when the

magnitude of the calibrated current value is too large or

too small to fit in the Instantaneous Current Register.

MATH

General computation Indicates that a divide operation overflowed. This can happen normally

in the course of computation. If this bit is asserted but no other bits are asserted, then there is

no error, and this bit should be ignored.

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