TSM2N100CP datasheet(2/6 Pages) TSC

2 / 6 page

TSM2N100CP

Taiwan Semiconductor

Version: A1606

ELECTRICAL SPECIFICATIONS (T

A = 25°C unless otherwise noted)

PARAMETER

CONDITIONS

SYMBOL

MIN

TYP

MAX

UNIT

Static

Drain-Source Breakdown Voltage

VGS = 0V, ID = 250µA

BVDSS

1000

Gate Threshold Voltage

VDS = VGS, ID = 250µA

VGS(TH)

3.5

4.5

5.5

Gate Body Leakage

VGS = ±30V, VDS = 0V

IGSS

±100

Zero Gate Voltage Drain Current

VDS = 1000V, VGS = 0V

IDSS

µA

Drain-Source On-State Resistance

(Note 4)

VGS = 10V, ID = 0.9A

RDS(on)

8.5

Dynamic

(Note 5)

Total Gate Charge

VDS = 800V, ID = 1.85A,

VGS = 10V

Gate-Source Charge

Qgs

Gate-Drain Charge

Qgd

Input Capacitance

VDS = 25V, VGS = 0V,

f = 1.0MHz

Ciss

625

Output Capacitance

Coss

Reverse Transfer Capacitance

Crss

Gate Resistance

f = 1.0MHz, open drain

2.2

Switching

(Note 6)

Turn-On Delay Time

VDD = 500V, RG = 25Ω,

ID = 0.9A, VGS = 10V

td(on)

Turn-On Rise Time

Turn-Off Delay Time

td(off)

Turn-Off Fall Time

Source-Drain Diode

Forward Voltage

(Note 4)

IS = 1.85A, VGS = 0V

VSD

1.4

Reverse Recovery Time

VR = 100V, IS = 1.85A

dIF/dt = 100A/μs

trr

359

Reverse Recovery Charge

Qrr

1.34

μC

Notes:

Current limited by package

Pulse width limited by the maximum junction temperature

L = 20mH, IAS = 1.4A, VDD = 50V, RG = 25Ω, Starting TJ = 25

Pulse test: PW

≤ 300µs, duty cycle ≤ 2%

For DESIGN AID ONLY, not subject to production testing.

Switching time is essentially independent of operating temperature.

ORDERING INFORMATION

PART NO.

PACKAGE

PACKING

TSM2N100CP ROG

TO-252 (DPAK)

2,500pcs / 13” Reel

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