AD9260AS datasheet(33/45 Pages) AD

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AD9260

Rev. C | Page 32 of 44

Table 15. Recommended Mode Pin Ranges

and Configurations

Mode Pin Range

Typical Mode Pin

Decimation Mode

0 V–0.5 V

GND

8×

0.5 V–1.5 V

VREF/2

2×

1.5 V–3.0 V

CML

4×

3.0 V–5.0 V

AVDD

1×

BIAS PIN OPERATION

The Bias Select Pin (BIAS) gives the user, who is able to operate

the AD9260 at a slower clock rate, the added flexibility of

running the device in a lower, power consumption mode when

it is clocked at less than 20 MHz.

This is accomplished by scaling the bias current of the AD9260

as illustrated in Figure 69. The bias amplifier drives a source

follower and forces 1 V across REXT, which sets the bias current.

This effectively adjusts the bias current in the modulator

amplifiers and FLASH preamplifiers. When a large value of REXT

is used, a smaller bias current is available to the internal

amplifier circuitry. As a result these amplifiers need more time

to settle, thus dictating the use of a slower clock as the power

is reduced. Refer to the characterization curves shown in Figure

47 to Figure 54 revealing the performance tradeoffs.

The scaling is accomplished by properly attaching an external

resistor to the BIAS pin of the AD9260 as shown in Table 17.

REXT is normally 2 kΩ for a clock speed of 20 MHz and scales

inversely with clock rate. Because BIAS is an external pin,

minimization of capacitance to this pin is recommended in

order to prevent instability of the bias pin amplifier.

AVDD

MODE PIN

AVSS

LATCH

CLOCK

ENCODED MODE

Figure 68. Simplified Mode Pin Circuitry

BIAS CURRENT

REXT

BIAS PIN

Figure 69. Simplified Bias Pin Circuitry

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