Functional Description
The CY7C4282/CY7C4292 are high-speed, low-power, FIFO memories with clocked read and write interfaces. All devices are nine bits wide. The CY7C4282/CY7C4292 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, video and communications buffering.

Features
• High-speed, low-power, first-in first-out (FIFO) memories
• 64K × 9 (CY7C4282)
• 128K × 9 (CY7C4292)
• 0.5-micron CMOS for optimum speed/power
• High-speed, near-zero latency (true dual-ported memory cell), 100-MHz operation (10-ns read/write cycle times)
• Low power
   — ICC=40 mA
   — ISB = 2 mA
• Fully asynchronous and simultaneous read and write operation
• Empty, Full, and Programmable Almost Empty and Almost Full status flags
• TTL-compatible
• Retransmit function
• Output Enable (OE) pin
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Depth-Expansion Capability through token-passing scheme (no external logic required)
• 64-pin 10 × 10 STQFP