56F8322/56F8122 General Description
Note: Features in italics are NOT available in the 56F8122 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified, C-efficient architecture
• 32KB Program Flash
• 4KB Program RAM
• 8KB Data Flash
• 8KB Data RAM
• 8KB Boot Flash
• One 6-channel PWM module
• Two 3-channel 12-bit ADCs
• Temperature Sensor
• One Quadrature Decoder
• FlexCAN module
• Up to two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Two general-purpose Quad Timers
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging
• Up to 21 GPIO lines
• 48-pin LQFP Package

56F8322/56F8122 Features
Hybrid Controller Core
• Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Four 36-bit accumulators, including extension bits
• Arithmetic and logic multi-bit shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses
• Four internal data buses
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/EOnCE debug programming interface

Memory
Note: Features in italics are NOT available in the 56F8122 device.
• Harvard architecture permits as many as three simultaneous accesses to program and data memory
• Flash security protection
• On-chip memory, including a low-cost, high-volume Flash solution
    — 32KB of Program Flash
    — 4KB of Program RAM
    — 8KB of Data Flash
    — 8KB of Data RAM
    — 8KB of Boot Flash
• EEPROM emulation capability