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SDA9401 bảng dữ liệu (PDF) - List of Unclassifed Manufacturers

SDA9401 Datasheet PDF - List of Unclassifed Manufacturers
tên linh kiện SDA9401
tải về  SDA9401 tải về
kích thước tập tin   1142.31 Kbytes
Page   69 Pages
nhà sản xuất  ETC [List of Unclassifed Manufacturers]
Trang chủ  
Logo ETC - List of Unclassifed Manufacturers
Giải thích chi tiết về linh kiện Scan Rate Converter using Embedded DRAM Technology Units

SDA9401 Datasheet (PDF)

Go To PDF Page tải về bảng dữ liệu
SDA9401 Datasheet PDF - List of Unclassifed Manufacturers

tên linh kiện SDA9401
tải về  SDA9401 Click to download

kích thước tập tin   1142.31 Kbytes
Page   69 Pages
nhà sản xuất  ETC [List of Unclassifed Manufacturers]
Trang chủ  
Logo ETC - List of Unclassifed Manufacturers
Giải thích chi tiết về linh kiện Scan Rate Converter using Embedded DRAM Technology Units

SDA9401 bảng dữ liệu (HTML) - List of Unclassifed Manufacturers


SDA9401 Thông tin chi tiết sản phẩm

[Micronas]

General description
The SDA 9401 is a new component of the Micronas MEGAVISION® IC set in a 0.35 µm embedded DRAM technology (field memory embedded). The SDA 9401 is pin compatible to the SDA 9400 (frame memory embedded). The SDA 9401 comprises all main functionalities of a digital featurebox in one monolithic IC.

Features
• Two input data formats
   - 4:2:2 luminance and chrominance parallel (2 x 8 wires)
   - ITU-R 656 data format (8 wires)
• Two different representations of input chrominance data
   - 2‘s complement code
   - Positive dual code
• Flexible input sync controller
• Flexible compression of the input signal
   - Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0)
   - Digital horizontal compression of the input signal (1.0, 2.0, 4.0)
• Noise reduction
   - Motion adaptive spatial and temporal noise reduction (3D-NR)
   - Temporal noise reduction for luminance field based
   - Temporal noise reduction for chrominance field based
   - Separate motion detectors for luminance and chrominance
   - Flexible programming of the temporal noise reduction parameters
   - Automatic measurement of the noise level (5 bit value, readable by I²C bus)
• TV mode detection by counting line numbers (PAL, NTSC, readable by I²C bus)
• Embedded memory
   - 3.2 Mbit embedded DRAM core for field memories
   - 128 kbit embedded DRAM core for line memories
• Flexible clock and synchronization concept
   - Decoupling of the input and output clock system possible
• Scan rate conversion
   - Simple 100/120 Hz interlaced scan conversion (e.g. AABB, AA*B*B)
   - Simple progressive scan conversion (e.g. AA*)
• Flexible digital vertical expansion of the output signal (1.0, ... [1/32] ... , 2.0)
• Flexible output sync controller
   - Flexible positioning of the output signal
   - Flexible programming of the output sync raster
• Signal manipulations
   - Insertion of coloured background
   - Vertical and/or horizontal windowing with four different speed factors
   - Flash generation
   - Still field
   - Support of split screen applications
   - Multiple picture display - Tuner scan (4 and 16 times for 4:3, 12 times for 16:9 tubes)
   - Support of multi picture display with PIP or front-end processor with integrated scaler
      (e.g. 9 times display of PIP pictures, picture tracking, random pictures, still-in-moving picture, moving-in-still picture)
• I²C-bus control (400 kHz)
• P-MQFP-64 package
• 3.3 V ± 5% supply voltage




Số phần tương tự - SDA9401

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