Description
The Intersil HIP7010, J1850 Byte Level Interface Circuit, is a member of the Intersil family of low-cost multiplexed wiring ICs. The integrated functions of the HIP7010 provide the system designer with components key to building a “Class B” multiplexed communications network interface, which fully conforms to the VPW Multiplexed Wiring protocol specified in the SAE J1850 Standard.

Features
• Fully Supports VPW (Variable Pulse Width) Messaging Practices of SAE J1850 Standard for Class B Data Communications Network Interface - 3-Wire, High-Speed, Synchronous, Serial Interface
• Reduces Wiring Overhead
• Directly Interfaces with 68HC05 and 68HC11 Style SPI Ports
• 1MHz, 8-Bit Transfers Between Host and HIP7010 Minimize Host Service Requirements
• Automatically Transmits Properly Framed Messages
• Prepends SOF to First Byte and Appends CRC to Last Byte
• Fail-Safe Design Including, Slow Clock Detection Circuitry, Prevents J1850 Bus Lockup Due to System Errors or Loss of Input Clock
• Automatic Collision Detection
• End of Data (EOD), Break, Idle Bus, and Invalid Symbol (Noise/Illegal Symbols) Detection
• Supports In-Frame Responses with Generation of Normalization Bits (NB) for Type 1, Type 2, and Type 3 Messages
• Wait-For-Idle Mode Reduces Host Overhead During Non-Applicable Messages
• Status Register Flags Provide Information on Current Status of J1850 Bus
• Serial I/O Pins are Active Only During Transfers - Bus Available for Other Devices 95% of the Time
• TEST Pin Provides Built-in-Test Capabilities for In-System Diagnostics and Factory Testing
• High Speed (4X) Receive Mode for Production and Diagnostic Testing/Programming
• Operates with Wide Range of Input Clock Frequencies
• Power-Saving Power-Down Mode
• Full -40oC to +125oC Operating Range
• Single 3.0V to 6.0V Supply