GENERAL DESCRIPTION
The AD9571 provides a multioutput clock generator function comprising a dedicated PLL core that is optimized for Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

FEATURES
   Fully integrated VCO/PLL core
      0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
      0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
      Input crystal or clock frequency of 25 MHz
   Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and
      125 MHz
   Choice of LVPECL or LVDS output format
   Integrated loop filter
   6 copies of reference clock output
   Rates configured via strapping pins
   Space saving 6 mm × 6 mm 40-lead LFCSP
   0.48 W power dissipation (LVDS operation)
   0.69 W power dissipation (LVPECL operation)
   3.3 V operation

APPLICATIONS
   Ethernet line cards, switches, and routers
   SCSI, SATA, and PCI-express
   PCI support included
   Low jitter, low phase noise clock generation