DESCRIPTION
TheM54/74HC137 is ahigh speed CMOS3TO8LINE DECODER/LATCH (INVERTING) fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption.

■ HIGH SPEED tPD = 11 ns (TYP.) AT VCC = 5 V
■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C
■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.)
■ OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS
■ SYMMETRICAL OUTPUT IMPEDANCE |IOH| = IOL = 4 mA (MIN.)
■ BALANCED PROPAGATION DELAYS tPLH = tPHL
■ WIDE OPERATING VOLTAGE RANGE VCC (OPR) = 2 V TO 6 V
■ PIN AND FUNCTION COMPATIBLE WITH 54/74LS137