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54SC1G175MDBVTSEP bảng dữ liệu (PDF) - Texas Instruments

54SC1G175MDBVTSEP Datasheet PDF - Texas Instruments
tên linh kiện 54SC1G175MDBVTSEP
tải về  54SC1G175MDBVTSEP tải về
kích thước tập tin   1015.6 Kbytes
Page   25 Pages
nhà sản xuất  TI2 [Texas Instruments]
Trang chủ  https://www.ti.com
Logo TI2 - Texas Instruments
Giải thích chi tiết về linh kiện SN54SC1G175-SEP Single D-Type Flip-Flop With Asynchronous Clear

54SC1G175MDBVTSEP Datasheet (PDF)

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54SC1G175MDBVTSEP Datasheet PDF - Texas Instruments

tên linh kiện 54SC1G175MDBVTSEP
tải về  54SC1G175MDBVTSEP Click to download

kích thước tập tin   1015.6 Kbytes
Page   25 Pages
nhà sản xuất  TI2 [Texas Instruments]
Trang chủ  https://www.ti.com
Logo TI2 - Texas Instruments
Giải thích chi tiết về linh kiện SN54SC1G175-SEP Single D-Type Flip-Flop With Asynchronous Clear

54SC1G175MDBVTSEP bảng dữ liệu (HTML) - Texas Instruments


54SC1G175MDBVTSEP Thông tin chi tiết sản phẩm

1 Features
• VID V62/26610
• Radiation - Total Ionizing Dose (TID):
– TID characterized up to 50krad(Si)
– TID performance assurance up to 30krad(Si)
– Radiation Lot Acceptance Testing (RLAT) for
every wafer lot up to 30krad(Si)
• Radiation - Single-Event Effects (SEE):
– Single Event Latch-Up (SEL) immune up to
50MeV-cm2/mg at 125°C
– Single Event Transient (SET) characterized up
to LET = 50MeV-cm2/mg
• Wide operating range of 1.2V to 5.5V
• 5.5V tolerant input pins
• Supports standard pinouts
• Up to 150Mbps with 5V or 3.3V VCC
• Latch-up performance exceeds 100mA per JESD
78
• Space enhanced plastic:
– Supports Defense and Aerospace Applications
– Controlled baseline
– Au bondwire and NiPdAu lead finish
– Meets NASA ASTM E595 outgassing
specification
– One fabrication, assembly, and test site
– Extended product life cycle
– Product traceability

2 Applications
• Enable or disable a digital signal
• Controlling an indicator LED

3 Description
The SN54SC1G175-SEP device is a single D-type
flip-flop with asynchronous clear (CLR) input. When
CLR is HIGH, data from the input pin (D) transfers to
the output pin (Q) on the clock's (CLK) rising edge.
When CLR is LOW, the Q is forced into the LOW
state, regardless of the clock edge or data on D.




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