FEATURES
1. ROM: 2K x 16 bits MTP(TM56M152A)
2. RAM: 128 x 8 bits
3. STACK: 8 Levels
4. System Clock type selections:
 Fast clock from Internal RC (FIRC, 16 MHz)
 Slow clock from Internal RC (SIRC, 93 KHz@VCC=5V)
5. System Clock Prescaler:
 System Clock can be divided by 1/2/4/8 option
6. Power Saving Operation Mode
 FAST Mode: Slow-clock is enabled, Fast-clock keeps CPU running
 SLOW Mode: Fast-clock can be disabled or enabled, Slow-clock keeps CPU running
 IDLE Mode: Fast-clock and CPU stop. Slow-clock or Wake-up Timer keep running
 STOP Mode: All clocks stop, Wake-up Timer stop
7. 2 Independent Timers
 Timer0
- 8-bit timer divided by 1~256 pre-scale option / auto-reload / counter / interrupt / stop function
 Timer1
- 8-bit timer divided by 1~256 pre-scale option / auto-reload / interrupt / stop function
- Overflow and Toggle out
8. Interrupt
 Three External Interrupt pins
- 1 pin is falling edge wake-up triggered & Interrupts
- 2 pins are rising or falling edge wake-up triggered & Interrupt
 Timer0 / Timer1 / Wake-up Timer Interrupt
 ADC Interrupt
 PWM Interrupt
 LVD Interrupt
 All Port Pin Change Wakeup Interrupts
9. Wake-up Timer (WKT)
 Clocked by built-in RC oscillator with 4 adjustable interrupt times
- 11 ms / 23 ms / 46 ms / 91 ms @VCC=5V
10. Watchdog Timer (WDT)
 Clocked by built-in RC oscillator with 4 adjustable reset times
- 91 ms / 183 ms / 732 ms / 1463 ms @VCC=5V
 Watchdog timer can be disabled / enabled in STOP mode
11. Six 16 bits PWMs
 Six individual duty-adjustable, shared period-adjustable
 PWM clock source: System clock (Fsys), FIRC/256, FIRC (16 MHz), FIRC*2 (32 MHz)
 PWM0 supports complementary output (PWM0P, PWM0N)
 PWM0 output with dead-zone(non-overlap) time durations adjustable: (0~15)*(PWMCLK)
 PWM0N/0P/1/2/3/5 has only one output
12. 12-bit ADC with 13 channels for External Pin Input and 2 channels for Internal Voltage
 Two internal voltage channels: VBG, 1/4VCC
 ADC reference voltage: VCC, VBG (1.2V), VBG (2.48V) and VBG (2V)
13. Reset Sources
 Power On Reset
 Watchdog Timer Reset
 Low Voltage Reset
 External Pin Reset
14. Low Voltage Reset (LVR) and Low Voltage Detection (LVD)
 15-Level Low Voltage Reset: 1.73V ~ 3.5V, can be disabled
 15-Level Low Voltage Detection: 1.73V ~ 3.5V, can be disabled
15. Operating Voltage
 Fsys= 16 MHz, LVR~5.5V. Suggest LVR ≥ 2.30V
 Fsys= 8 MHz, PWMCKS=FIRC*1, LVR~5.5V. Suggest LVR ≥ 1.55V
Note: Refer to the “Electrical Characteristics Graphs”.
16. Operating Temperature Range : -40°C to + 105°C
17. Table Read Instruction: 16-bit ROM data lookup table
18. Integrated 16-bit Cyclic Redundancy Check (CRC) function
19. Instruction set: 39 Instructions
20. I/O ports:
 Maximum 14 programmable I/O pins
- Open-Drain Output
- CMOS Push-Pull Output
- Schmitt Trigger Input with pull-up resistor option
- All I/O with High-Sink except PA7
 All pin change wake up (falling edge and rising edge trigger) and interrupt
21. Programming connectivity support 5-wire (ICP) or 7-wire program
22. RDCTL: Read signal delay control for Program ROM
 The user must switch this register to “4ns” to enhance the performance of minimal operating
voltage.
23. Trimmed VBG1.2V/2V
 The users could move BG2TRIM to BGTRIM for exact 2V VBG.
24. ATD: Automatic transient detection to enhance the performance of power consumption at slow
mode
25. Package Types:
 16-pin SOP (150 mil)
 14-pin SOP (150 mil)
 10-pin MSOP (118 mil)
 8-pin SOP (150 mil)
 16-pin QFN (3*3*0.75 - 0.5mm)
 10-pin DFN (3*3*0.75 - 0.5mm)
26. Supported EV board
 TM56F1552/22