1 Features
• High-performance LVDS clock buffer family with 2
inputs and 4 outputs (2:4)
• Output frequency up to 2 GHz
• Hardware pins for individual output enable/disable
• Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
• Low additive jitter: < 60 fs rms maximum in 12 kHz
to 20 MHz at 156.25 MHz
– Very low phase noise floor: -164 dBc/Hz
(typical)
• Very low propagation delay: < 575 ps maximum
• Output skew: 20 ps maximum
• Fail-safe inputs
• Universal inputs accept LVDS, LVPECL, LVCMOS,
HCSL and CML
• LVDS reference voltage, VAC_REF, available for
capacitive-coupled inputs
• Industrial temperature range: –40°C to 105°C
• Packages available:
– 5-mm × 5-mm, 28-pin VQFN (RHD)

2 Applications
• Telecommunications and networking
• Medical imaging
• Test and measurement
• Wireless infrastructure
• Pro audio, video and signage

3 Description
The LMK1D1204P clock buffer distributes one of two
selectable clock inputs (IN0 and IN1) to 4 pairs of
differential LVDS clock outputs (OUT0 through OUT3)
with minimum skew for clock distribution. The inputs
can be either LVDS, LVPECL, LVCMOS, HCSL, or
CML.
The LMK1D1204P is specifically designed for driving
50-Ω transmission lines. When driving inputs in
single-ended mode, apply the appropriate bias
voltage to the unused negative input pin (see Figure
9-6). The IN_SEL pin selects the input which is routed
to the outputs. The part supports a fail-safe input
function. The device further incorporates an input
hysteresis which prevents random oscillation of the
outputs in the absence of an input signal.
Each LVDS differential output is enabled by setting
the corresponding OEx pin to a logic high "1". If this
pin is set to a logic low "0", the output is disabled in a
high Z state resulting in reduced power consumption.
The device operates in a 1.8-V, 2.5-V, or 3.3-V
supply environment and is characterized from –40°C
to 105°C (ambient temperature).