x
Highest Performance Floating-Point Digital
Signal Processor (DSP)
– ’320C40-60:
33-ns Instruction Cycle Time,
330 MOPS, 60 MFLOPS,
30 MIPS, 384M Bytes/s
– ’320C40-50:
40-ns Instruction Cycle Time
– ’320C40-40:
50-ns Instruction Cycle Time
Six Communications Ports
Six-Channel Direct Memory Access (DMA)
Coprocessor
Single-Cycle Conversion to and From
IEEE-754 Floating-Point Format
Single Cycle, 1/x, 1/
Source-Code Compatible With TMS320C3x
Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
Twelve 40-Bit Registers, Eight Auxiliary
Registers, 14 Control Registers, and Two
Timers
IEEE 1149.1† (JTAG) Boundary Scan
Compatible
Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
– High Port-Data Rate of 120M Bytes/s
(’C40-60) (Each Bus)
– 16G-Byte Continuous
Program/Data/Peripheral Address
Space
– Memory-Access Request for Fast,
Intelligent Bus Arbitration
– Separate Address-Bus, Data-Bus, and
Control-Enable Pins
– Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
325-Pin Ceramic Grid Array (GF Suffix)
Fabricated Using 0.72-mm Enhanced
Performance Implanted CMOS (EPICE)
Technology by Texas Instruments (TIE)
Software-Communication-Port Reset
NMI With Bus-Grant Feature
Separate Internal Program, Data, and DMA
Coprocessor Buses for Support of Massive
Concurrent Input/Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance
On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
– 512-Byte Instruction Cache
– 8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
– ROM-Based Boot Loader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories or One of the Communication
Ports
IDLE2 Clock-Stop Power-Down Mode
5-V Operation