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MH64D72KLG-10 bảng dữ liệu (PDF) - Mitsubishi Electric Semiconductor

MH64D72KLG-10 Datasheet PDF - Mitsubishi Electric Semiconductor
tên linh kiện MH64D72KLG-10
tải về  MH64D72KLG-10 tải về
kích thước tập tin   326.71 Kbytes
Page   38 Pages
nhà sản xuất  MITSUBISHI [Mitsubishi Electric Semiconductor]
Trang chủ  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Giải thích chi tiết về linh kiện 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MH64D72KLG-10 Datasheet (PDF)

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MH64D72KLG-10 Datasheet PDF - Mitsubishi Electric Semiconductor

tên linh kiện MH64D72KLG-10
tải về  MH64D72KLG-10 Click to download

kích thước tập tin   326.71 Kbytes
Page   38 Pages
nhà sản xuất  MITSUBISHI [Mitsubishi Electric Semiconductor]
Trang chủ  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Giải thích chi tiết về linh kiện 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MH64D72KLG-10 bảng dữ liệu (HTML) - Mitsubishi Electric Semiconductor


MH64D72KLG-10 Thông tin chi tiết sản phẩm

DESCRIPTION
The MH64D72KLG is 67108864 - word x 72-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module. This consists of 18 industry standard 64M x 4 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz. This socket-ty pe memory module is suitable f or main memory in computer systems and easy to interchange or add modules.

FEATURES
- Utilizes industry standard 64M X 4 DDR Synchronous DRAMs in TSOP package , industry standard Registered Buffer in TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed with data
- Dif f erential clock inputs (CLK and /CLK)
- data ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9,11
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge

APPLICATION
    Main memoryunit for PC, PC server, Server, W S.




Số phần tương tự - MH64D72KLG-10

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Mitsubishi Electric Sem...
MH64D72KLH-10 MITSUBISHI-MH64D72KLH-10 Datasheet
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4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH64D72KLH-75 MITSUBISHI-MH64D72KLH-75 Datasheet
350Kb / 39P
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
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Mô tả tương tự - MH64D72KLG-10

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