The i.MX RT500 is a family of dual-core microcontrollers for
embedded applications featuring an Arm Cortex-M33 CPU
combined with a Cadence® Xtensa® Fusion F1 Audio Digital
Signal Processor CPU. The Cortex-M33 includes two hardware
coprocessors providing enhanced performance for an array of
complex algorithms along with a 2D Vector GPU with LCD
Interface and MIPI DSI PHY. The family offers a rich set of
peripherals and very low power consumption. The device has up
to 5 MB SRAM, two FlexSPIs (Octal/Quad SPI Interfaces) each
with 32 KB cache, one with dynamic decryption, high-speed USB
device/host + PHY, 12-bit 1 MS/s ADC, Analog Comparator,
Audio subsystems supporting up to 8 DMIC channels, 2D GPU
and LCD Controller with MIPI DSI PHY, SDIO/eMMC; FlexIO;
AES/SHA/Crypto M33 coprocessor and PUF key generation

Control processor core
• Arm Cortex-M33 processor, running at frequencies of
up to 275 MHz
• Arm TrustZone
• Arm Cortex-M33 built-in Memory Protection Unit (MPU)
supporting eight regions
• Single-precision Hardware Floating Point Unit (FPU).
• Arm Cortex-M33 built-in Nested Vectored Interrupt
Controller (NVIC).
• Non-maskable Interrupt (NMI) input.
• Two coprocessors for the Cortex-M33: a hardware
accelerator for fixed and floating point DSP functions
(PowerQuad) and a Crypto/FFT engine (Casper). The
DSP coprocessor uses a bank of four dedicated 8 KB
SRAMs. The Crypto/FFT engine uses a bank of two 2
KB SRAMs that are also AHB accessible by the CPU
and the DMA engine.
• Serial Wire Debug with eight break points, four watch
points, and a debug timestamp counter. It includes
Serial Wire Output (SWO) trace and ETM trace.
• Cortex-M33 System tick timer
DSP processor core
• Cadence Tensilica Fusion F1 DSP processor, running
at frequencies of up to 275 MHz.
• Hardware Floating Point Unit.
• Serial Wire Debug (shared with Cortex-M33 Control
Domain CPU).
Communication interface
• Up to 9-12 configurable universal serial interface
modules (Flexcomm Interfaces). Each module
contains an integrated FIFO and DMA support.
Each of the nine modules can be configured as:
• A USART with dedicated fractional baud rate
generation and flow-control handshaking
signals. The USART can optionally be clocked
at 32 kHz and operated when the chip is in
reduced power mode, using either the 32 kHz
clock or an externally supplied clock. The
USART also provides partial support for
LIN2.2.
• An I2C-bus interface with multiple address
recognition, and a monitor mode. It supports
400 Kb/sec Fast-mode and 1 Mb/sec Fastmode
Plus. It also supports 3.4 Mb/sec highspeed
when operating in slave mode.
• An SPI interface.
• An I2S (Inter-IC Sound) interface for digital
audio input or output. Each I2S supports up to
four channel-pairs.
• Two additional high-speed SPI interfaces supporting
50 MHz operation
• One additional I2C interface with open-drain pads
• Two I3C bus interfaces
• A digital microphone interface supporting up to 8
channels with associated decimators and Voice