1 Features
• FMCW transceiver
– Integrated PLL, transmitter, receiver, baseband
and ADC
– 76 to 81-GHz coverage with greater than 4 GHz
available bandwidth
– 4 receive and 4 transmit channels with
Launch-on-Package (LOP) interface to
antennas
– Per transmit phase shifter
– Ultra-accurate chirp engine based on fractional
PLL
– TX power
• +12 dBm
– RX noise figure
• +13 dB
– Phase noise (@ 1MHz)
• -96 dBc/Hz (76 to 77GHz)
• -95 dBc/Hz (76 to 81GHz)
• Built-in calibration and self-test
– Built in firmware (ROM)
– Self-calibrating system across process and
temperature
• Processing elements
– Arm® Cortex-R5F® core (supports lock step
operation) at 300 MHz
– TI radar hardware accelerator (HWA1.5) for
operations like FFT, interference mitigation, and
memory compression
– Multiple EDMA instances for data movement
• Host interface
– 10/100/1000Mbps RGMII/RMII/MII Ethernet
– 25MHz clock output for Ethernet PHY clocking
• Supports a serial flash memory interface (loading
user application from QSPI flash memory)
• Other interfaces available to user application
– Up to 4 ADC channels
– 1 SPI
– 2 UARTs
– I2C
– GPIOs
– 3 EPWMs
– 2-lane LVDS interface for raw ADC data and
debug instrumentation
• On-Chip RAM
– 2MB
– Memory space split between MCU and shared
L3
• Device security (on select part numbers)
– Programmable embedded hardware security
module (HSM)
– Secure authenticated and encrypted boot
support
– Customer programmable root keys, symmetric
keys (256 bit), asymmetric keys (up to RSA-4K
or ECC-512) with key revocation capability
– Cryptographic hardware accelerators: PKA with
ECC, AES (up to 256 bit), SHA (up to 512 bit),
TRNG/DRBG
• Functional safety compliant targeted
– Developed for functional safety applications
– Documentation available to aid ISO26262
functional safety system design
– Hardware integrity up to ASIL B targeted
• AEC-Q100 qualified
• Advanced features
– Embedded self-monitoring with no external
processor involvement
– Embedded interference detection capability
• Power management
– On-die LDO network for enhanced PSRR
– LVCMOS IO supports dual voltage 3.3 V and
1.8 V
• Clock source
– 40MHz or 50MHz crystal with internal oscillator
– Supports external oscillator/driven clock at 40
MHz or 50 MHz
• Power Management
– Recommended LP8772-Q1 Power
Management IC (PMIC)
• Companion PMIC specially designed to
meet device power supply requirements
• Flexible mapping and factory programmed
configurations to support different use cases
• Cost-reduced hardware design
– 0.65-mm pitch, 12.4-mm × 12-mm FCSSP
package
– Small size
• Supports automotive temperature operating range
– Operating junction temperature range: –40°C to
+140°C

2 Applications
• Lane change assist
• Blind spot detection
• Automatic emergency braking
• Adaptive cruise control
• Cross traffic alert
• Satellite

3 Description
The AWR2544 is a single-chip mmWave sensor composed of a FMCW transceiver. The device is capable of
operation in the 76 to 81GHz (EHF) band, includes radar data processing elements, and a rich set of peripherals
for in-vehicle networking. AWR2544 provides customers with an additional Launch on package (LOP) antenna
feature which facilitates the attachment of antennas directly on to the package. The AWR2544 is built with TI’s
low-power 45 nm RFCMOS process and enables unprecedented levels of integration in a small form factor and
minimal BOM. The AWR2544 is designed for low-power, self-monitored, ultra-accurate radar systems in the
automotive space.
TI’s low-power 45nm RFCMOS process enables a monolithic implementation of a 4 TX, 4 RX system with
integrated PLL, VCO, mixer, and baseband ADC. The device includes a Radio Processor Subsystem (RSS),
which is responsible for radar front-end configuration, control, and calibration. Within the Main Subsystem
(MSS), the device implements a user-programmable Arm Cortex-R5F processor allowing for custom control
and automotive interface applications. The hardware accelerator block (HWA 1.5) supplements the MSS by
offloading common radar processing such as FFT, scaling, and compression. This saves MIPS on the external
processor, opening up resources for custom applications and implementation of higher-level post-processing
algorithms.
A Hardware Security Module (HSM) is also provisioned in the device (available for only secure part variants).
The HSM consists of a programmable Arm Cortex-M4 core and the necessary infrastructure to provide a secure
zone of operation within the device.