1. General description
The 74AVC8T245 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It
features two 8-bit input-output ports (An and Bn), a direction control input (DIR), a output enable
input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any
voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low
voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIR are referenced to
VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and
a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn
are in the high-impedance OFF-state.
2. Features and benefits
• Wide supply voltage range:
• VCC(A): 0.8 V to 3.6 V
• VCC(B): 0.8 V to 3.6 V
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8-B (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114E Class 3B exceeds 8000 V
• MM JESD22-A115-A exceeds 200 V
• CDM JESD22-C101C exceeds 1000 V
• Maximum data rates:
• 380 Mbit/s (≥ 1.8 V to 3.3 V translation)
• 260 Mbit/s (≥ 1.1 V to 3.3 V translation)
• 260 Mbit/s (≥ 1.1 V to 2.5 V translation)
• 210 Mbit/s (≥ 1.1 V to 1.8 V translation)
• 150 Mbit/s (≥ 1.1 V to 1.5 V translation)
• 100 Mbit/s (≥ 1.1 V to 1.2 V translation)
• Suspend mode
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• IOFF circuitry provides partial Power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C