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74AVCH2T45DC bảng dữ liệu (PDF) - Nexperia B.V. All rights reserved

74AVCH2T45DC Datasheet PDF - Nexperia B.V. All rights reserved
tên linh kiện 74AVCH2T45DC
tải về  74AVCH2T45DC tải về
kích thước tập tin   340.09 Kbytes
Page   22 Pages
nhà sản xuất  NEXPERIA [Nexperia B.V. All rights reserved]
Trang chủ  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
Giải thích chi tiết về linh kiện Dual-bit, dual-supply voltage level translator/transceiver; 3-state

74AVCH2T45DC Datasheet (PDF)

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74AVCH2T45DC Datasheet PDF - Nexperia B.V. All rights reserved

tên linh kiện 74AVCH2T45DC
tải về  74AVCH2T45DC Click to download

kích thước tập tin   340.09 Kbytes
Page   22 Pages
nhà sản xuất  NEXPERIA [Nexperia B.V. All rights reserved]
Trang chủ  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved
Giải thích chi tiết về linh kiện Dual-bit, dual-supply voltage level translator/transceiver; 3-state

74AVCH2T45DC bảng dữ liệu (HTML) - Nexperia B.V. All rights reserved


74AVCH2T45DC Thông tin chi tiết sản phẩm

1. General description
The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation.
It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply
pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V
and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V,
1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are
referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows
transmission from nB to nA.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry
disables the output, preventing any damaging backflow current through the device when it is
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are
in the high-impedance OFF-state.
The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data
inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down
resistors.
2. Features and benefits
• Wide supply voltage range: 0.8 V to 3.6 V for VCC(A) and VCC(B)
• High noise immunity
• Suspend mode
• Bus hold on data inputs
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial Power-down mode operation
• Maximum data rates:
• 500 Mbps (1.8 V to 3.3 V translation)
• 320 Mbps (< 1.8 V to 3.3 V translation)
• 320 Mbps (translate to 2.5 V or 1.8 V)
• 280 Mbps (translate to 1.5 V)
• 240 Mbps (translate to 1.2 V)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Complies with JEDEC standards:
• JESD8-12 (0.8 V to 1.3 V)
• JESD8-11 (0.9 V to 1.65 V)
• JESD8-7 (1.2 V to 1.95 V)
• JESD8-5 (1.8 V to 2.7 V)
• JESD8-B (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/Jedec JS-001 Class 3B exceeds 8000 V
• CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C




Số phần tương tự - 74AVCH2T45DC

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
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Mô tả tương tự - 74AVCH2T45DC

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
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74AVC2T45 NXP-74AVC2T45 Datasheet
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Rev. 01 - 3 July 2007
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