1 Features
• Operating range of 4.5 V to 5.5 V
• Low power consumption, 10-μA maximum ICC
• ±8-mA output drive at 5 V
• Inputs are TTL-voltage compatible
• Latch-up performance exceeds 250 mA per JESD
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2 Applications
• Convert a momentary switch to a toggle switch
• Hold a signal during controller reset
• Input slow edge-rate signals
• Operate in noisy environments
• Divide a clock signal by two

3 Description
The ’AHCT74 dual positive-edge-triggered devices
are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on
the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.