Features
• Wide clock frequency range from 20 MHz to 100 MHz
• Pin compatible with the National DS90CF386, THine
THC63LVDF84, TISN65LVDS94
• Converts 4-pair LVDS data streams into parallel 28 bits of
CMOS/TTL data
• Fully spread spectrum compatible
• LVDS voltage swing of 350 mV for low EMI
• On-chip PLL requires no external components
• Low-power CMOS design
• Falling edge clock triggered outputs
• Power-down control function
• Compatible with TIA/EIA-644 LVDS standards
• Packaged in a 56-pin TSSOP (Pb free available)