Description
Output Features
DDR Zero Delay Clock Buffer
• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input
Key Specifications
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<110ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 650ps - 950ps
• DUTY CYCLE: 49.5% - 50.5%