FEATURES
• Eight LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable CLK1, nCLK1 or LVCMOS/LVTTL clock inputs
• CLK1, nCLK1 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• CLK0 input accepts LVCMOS or LVTTL input levels
• Output frequency range: 15.625MHz to 250MHz
• Input frequency range: 15.625MHz to 250MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with confi gurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Fully integrated PLL
• Cycle-to-cycle jitter: 45ps (maximum)
• Output skew: CLK0, 65ps (maximum)
CLK1, nCLK1, 55ps (maximum)
• Static Phase Offset: 25 ±125ps (maximum), CLK0
• Full 3.3V or 2.5V operating supply
• Lead-Free package available
• -40°C to 85°C ambient operating temperature
• Not Recommended for New Designs
For new designs, contact IDT.