General Description
The 874328I-01 is a high-performance differential ÷1 and ÷4 clock
divider and fanout buffer. The device is designed for the
frequency-division and signal fanout of high-frequency, low
phase-noise clock signals. The differential input signal is frequency
divided by ÷1 and ÷4. Three LVPECL and three LVDS output banks
are provided with a total of twenty differential outputs. The
874328I-01 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 874328I-01 ideal for those clock distribution applications
demanding well-defined performance and repeatability.

Features
• One differential input LVPECL reference clock
• Differential pair can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
• Integrated input termination resistors
• One bank of three LVPECL outputs (÷1 frequency-divided)
• One bank of three LVPECL outputs (÷4 frequency-divided)
• One bank of two LVPECL outputs (÷4 frequency-divided)
• Two banks of three LVDS outputs (÷4 frequency-divided)
• One bank of six LVDS outputs (÷4 frequency-divided)
• Total of twenty differential clock outputs
• Maximum input frequency: 650MHz
• Maximum output frequency: 650MHz (÷1 outputs)
• Maximum output frequency: 162.5MHz (÷4 outputs)
• LVCMOS interface levels for all control inputs
• Output skew: 70ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Full 2.5V supply voltage
• Available in lead-free (RoHS 6) package
• -40°C to 85°C ambient operating temperature