Features
▪ Close-in phase noise complies with Common Public Radio
Interface (CPRI) frequency synchronization requirements
▪ Supports all ITU-T G.709 frequencies
▪ Meets OTN jitter and wander requirements per ITU-T G.8251
▪ Four independent timing channels
• Each can act as a frequency synthesizer, jitter attenuator,
Digitally Controlled Oscillator (DCO), or Digital Phase Lock
Loop (DPLL)
• DPLL Digital Loop Filters (DLFs) are programmable with cut
off frequencies from 1.1Hz to 22kHz
• Generates output frequencies that are independent of input
frequencies via a Fractional Output Divider (FOD)
• Each FOD supports output phase tuning with 50ps
resolution
▪ Four differential / eight LVCMOS outputs
• Frequencies from 0.5Hz to 1GHz (250MHz for LVCMOS)
• Jitter below 150fs RMS (10kHz to 20MHz)
• LVCMOS, LVDS, LVPECL, HCSL, CML, SSTL, and HSTL
output modes supported
• Differential output swing is selectable: 400mV / 650mV /
800mV / 910mV
• Independent output voltages of 3.3V, 2.5V, or 1.8V
▪ LVCMOS additionally supports 1.5V or 1.2V
• The clock phase of each output is individually programmable
in 1ns to 2ns steps with a total range of ±180°
▪ Two differential / four single-ended clock inputs
• Support frequencies from 1kHz to 1GHz
• Any input can be mapped to any or all of the timing channels
• Redundant inputs frequency independent of each other
• Any input can be designated as external frame/sync pulse of
PPES (pulse per even second), 1 PPS (Pulse per Second),
5PPS, 10 PPS, 50Hz, 100Hz, 1 kHz, 2 kHz, 4kHz, and 8kHz
associated with a selectable reference clock input
• Per-input programmable phase offset of up to ±1.638s in
50ps steps
▪ Reference monitors qualify/disqualify references depending on
LOS, activity, frequency monitoring, and/or LOS input pins
• Loss of Signal (LOS) input pins (via GPIOs) can be assigned
to any input clock reference
▪ Automatic reference selection state machines select the active
reference for each DPLL based on the reference monitors,
priority tables, revertive / non-revertive, and other
programmable settings
▪ System APLL operates from fundamental-mode crystal: 25MHz
to 54MHz or from a crystal oscillator
▪ System DPLL accepts an XO, TCXO, or OCXO operating at
virtually any frequency from 1MHz to 150MHz
▪ DPLLs can be configured as DCOs to synthesize clocks under
the control of an external algorithm
• DCOs generate PTP based clocks with frequency resolution
less than 1.11 × 10-16
▪ Supports 1MHz I2
C or 50MHz SPI serial processor ports
▪ The device can configure itself automatically after reset via:
• Internal customer definable One-Time Programmable
memory with up to 16 different configurations
• Standard external I2
C EPROM via separate I2
C Master Port
▪ 1149.1 JTAG Boundary Scan
▪ 7 × 7 mm 48-VFQFPN package

Description
The 8A34043 Four-Channel Universal Frequency Translator is a highly integrated timing device that generates synchronous or
asynchronous clocks from any of its reference inputs. The can be used in any synthesizer or jitter attenuator application, including Optical
Transport Network (OTN) and Synchronous Ethernet (SyncE) systems.
The internal System APLL must be supplied with a low phase noise reference clock with frequency between 25MHz and 54MHz. The
output of the System APLL is used for clock synthesis by all of the Fractional Output Dividers (FODs) in the device. The System APLL
reference can come from an external crystal oscillator connected to the OSCI pin or from an internal oscillator that uses a crystal
connected between the OSCI and OSCO pins.
The System DPLL generates an internal system clock that is used by the reference monitors and other digital circuitry in the device. If the
reference provided to the System APLL meets the stability and accuracy requirements of the intended application then the System DPLL
can free run and a System DPLL reference is not required. Alternatively, the System DPLL can be locked to an external reference that
meets the stability and accuracy requirements of the intended application. The System DPLL can accept a reference from the XO_DPLL
pin or via the reference selection mux.
The frequency accuracy/stability of the internal system clock determines the frequency accuracy/stability of the DPLLs in Free-Run mode
and in Holdover mode; and it affects the wander generation of the DPLLs in Locked and DCO modes. When provided with a suitably
stable and accurate system clock, the DPLLs meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise tolerance,
transient response, and holdover performance requirements of ITU-T G.8262 synchronous Ethernet Equipment Clock (EEC) options 1
and 2.