Functional Description[1]
The CY7C1214F is a 32,768 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access.

Features
• 32K X 32 common I/O
• 3.3V –5% and +10% core power supply (VDD)
• 3.3V I/O supply (VDDQ)
• Fast clock-to-output times
    — 7.5 ns (117-MHz version)
    — 8.5 ns (100-MHz version)
• Provide high-performance 2-1-1-1 access rate
• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed write
• Asynchronous output enable
• Supports 3.3V I/O level
• Offered in JEDEC-standard 100-pin TQFP package
• “ZZ” Sleep Mode option