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WC32P040-XXM bảng dữ liệu (PDF) - White Electronic Designs Corporation

WC32P040-XXM Datasheet PDF - White Electronic Designs Corporation
tên linh kiện WC32P040-XXM
tải về  WC32P040-XXM tải về
kích thước tập tin   726.71 Kbytes
Page   23 Pages
nhà sản xuất  WEDC [White Electronic Designs Corporation]
Trang chủ  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation
Giải thích chi tiết về linh kiện 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

WC32P040-XXM Datasheet (PDF)

Go To PDF Page tải về bảng dữ liệu
WC32P040-XXM Datasheet PDF - White Electronic Designs Corporation

tên linh kiện WC32P040-XXM
tải về  WC32P040-XXM Click to download

kích thước tập tin   726.71 Kbytes
Page   23 Pages
nhà sản xuất  WEDC [White Electronic Designs Corporation]
Trang chủ  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation
Giải thích chi tiết về linh kiện 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

WC32P040-XXM bảng dữ liệu (HTML) - White Electronic Designs Corporation


WC32P040-XXM Thông tin chi tiết sản phẩm

DESCRIPTION
The WC32P040 is a 68000-compatible, high-performance, 32-bit microprocessor. The WC32P040 is a virtual memory microprocessor employing multiple concurrent execution units and a highly intergrated architecture that provides very high performance in a monolithic HCMOS device. It has a 68030-compatible integer unit (IU) and two independent caches. The WC32P040 contains dual, independent, demand-paged memory management units (MMUs) for instruction and data stream accesses and independent, 4-Kbyte instruction and data caches. The WC32P040 has a 68881/68882-compatible fl oating-point unit (FPU).

68040 FEATURES
■ Selection of Processor Speeds: 25, 33MHz
■ Military Temperature Range: -55°C to +125°C
■ Packaging
    • 179 pin Ceramic PGA (P4)
    • 184 lead Ceramic Quad Flatpack, CQFP (Q4)
■ 6-Stage Pipeline, 68030-Compatible IU
■ 68881/68882-Compatible FPU
■ Independent Instruction and Data MMUs
■ Simultaneously Accessible, 4-Kbyte Physical Instruction Cache and 4-Kbyte Physical Data Cache
■ Low-Latency Bus Acceses for Reduced Cache Miss Penalty
■ Multimaster/Multiprocessor Support via Bus Snooping
■ Concurrent IU, FPU, MMU, and Bus Controller Operation Maximizes Throughput
■ 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface
■ User Object-Code Compatible with all Earlier 68000 Microprocessors
■ 4-GigaByte Direct Addressing Rang




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