1 Features
• 14-Bit, dual channel 2.6/3.0-GSPS ADC
• Noise spectral density:
– NSD = -155.6 dBFS/Hz (no AVG)
– NSD = -158.1 dBFS/Hz (2x AVG)
– NSD = -160.4 dBFS/Hz (4x AVG)
• Single core (non-interleaved) ADC architecture
• Aperture jitter: 50 fs
• Low close-in residual phase noise:
– -127 dBc/Hz at 10 kHz offset
• Spectral performance (fIN = 1 GHz, -4 dBFS):
– 2x internal averaging
– SNR: 62.3 dBFS
– SFDR HD2,3: 63 dBc
– SFDR worst spur: 85 dBFS
• Spectral performance (fIN = 1.8 GHz, -4 dBFS):
– 2x internal averaging
– SNR: 63.0 dBFS
– SFDR HD2,3: 68 dBc
– SFDR worst spur: 86 dBFS
• Input fullscale: 1.1/1.35 Vpp (2/3.5 dBm)
• Code error rate (CER): 10-15
• Full power input bandwidth (-3 dB): 2.75 GHz
• JESD204B serial data interface
– Maximum lane rate: 13 Gbps
– Supports subclass 1 deterministic latency
• Digital down-converters
– Up to four DDC per ADC channel
– Complex output: 4x to 128x decimation
– 48-bit NCO phase coherent frequency hopping
– Fast frequency hopping: < 1 us
• Power consumption: 2.6 W/channel (2x AVG)
• Power supplies: 1.8 V, 1.2 V

2 Applications
• Phased array radar
• Spectrum analyzer
• Software defined radio (SDR)
• Electronic warfare
• High-speed digitizer
• Cable infrastructure
• Communications infrastructure

3 Description
The ADC32RF5x is a single core 14-bit, 2.6
GSPS to 3 GSPS, dual channel analog to digital
converters (ADC) that supports RF sampling with
input frequencies up to 3 GHz. The design maximizes
signal-to-noise ratio (SNR) and delivers a noise
spectral density of -155 dBFS/Hz. Using additional
internal ADCs along with on-chip signal averaging, the
noise density improves to -161 dBFS/Hz.
Each ADC channel can be connected to a quad-band
digital down-converter (DDC) using a 48-bit NCO
which supports phase coherent frequency hopping.
Using the GPIO pins for NCO frequency control,
frequency hopping can be achieved in less than 1 μs.
The ADC32RF54 and ADC32RF55 supports the
JESD204B serial data interface with subclass 1
deterministic latency using data rates up to 13 Gbps.
The power efficient ADC architecture consumes 2.1
W/ch at 3 Gsps and provides power scaling with lower
sampling rates.