Description
The SA-1110 is a general-purpose, 32-bit RISC microprocessor with a 16 Kbyte instruction cache (Icache), an 8 Kbyte write-back data cache (Dcache), a minicache, a write buffer, a read buffer, an MMU, an LCD controller, and serial I/O combined in a single component. The SA-1110 provides portable applications with high-end computing performance without requiring users to sacrifice available battery time. Its power-management functionality provides further power savings. For embedded applications, the SA-1110 offers high-performance computing at consumer electronics pricing with MIPS-per-dollar and MIPS-per-watt advantages. The SA-1110 delivers in price/performance and power/performance, making it a chice for portable and embedded applications. The SA-1110 differs from the Intel® StrongARM SA-1100 Microprocessor (SA-1100) only in the features of its memory and PCMCIA controller.

Product Features
■ High performance
    —150 Dhrystone 2.1 MIPS @ 133 MHz
    —235 Dhrystone 2.1 MIPS @ 206 MHz
■ Memory bus
    —Interfaces to ROM, synchronous mask
        ROM (SMROM), Flash, SRAM, SRAM-like variable latency I/O, DRAM, and synchronous DRAM (SDRAM)
    —Supports two PCMCIA sockets
■ Low power (normal mode) †
    —<240 mW @1.55 V/133 MHz
    —<400 mW @1.75 V/206 MHz
■ 32-way set-associative caches
    —16 Kbyte instruction cache
    —8 Kbyte write-back data cache
■ Integrated clock generation
    —Internal phase-locked loop (PLL)
    —3.686-MHz oscillator
    —32.768-kHz oscillator
■ 32-entry MMUs
    —Maps 4 Kbyte, 8 Kbyte, or 1 Mbyte
■ Power-management features
    —Normal (full-on) mode
    —Idle (power-down) mode
    —Sleep (power-down) mode
■ Write buffer
    —8-entry, between 1 and 16 bytes each
■ Big and little endian operating modes
■ Read buffer
    —4-entry, 1, 4, or 8 words
■ 3.3-V I/O interface
■ 256 mini-ball grid array (mBGA)