PRODUCT DESCRIPTION

The SST49LF004B flash memory devices are designed to interface with host controllers (chipsets) that support a low pin-count (LPC) interface for BIOS applications. The SST49LF004B devices comply with Intel’s LPC Interface Specification, supporting single-byte Firmware Memory cycle type.

The SST49LF004B devices are backward compatible to the SST49LF004A Firmware Hub. In this document, FWH mode in the SST49LF004A specification is referenced as the Firmware Memory Read/Write cycle. Two interface modes are supported by the SST49LF004B: LPC mode (Firmware Memory cycle types) for in-system operations and Parallel Programming (PP) mode to interface with programming equipment.

FEATURES:

• 4 Mbit SuperFlash memory array for code/data storage

   – SST49LF004B: 512K x8 (4 Mbit)

• Conforms to Intel LPC Interface Specification

   – Supports Single-Byte Firmware Memory Cycle Type

• Flexible Erase Capability

   – Uniform 4 KByte sectors

   – Uniform 64 KByte overlay blocks

   – Chip-Erase for PP Mode Only

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

   – Endurance: 100,000 Cycles (typical)

   – Greater than 100 years Data Retention

• Low Power Consumption

   – Active Read Current: 6 mA (typical)

   – Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

   – Sector-Erase Time: 18 ms (typical)

   – Block-Erase Time: 18 ms (typical)

   – Chip-Erase Time: 70 ms (typical)

   – Byte-Program Time: 14 µs (typical)

   – Chip Rewrite Time: 8 seconds (typical)

   – Single-pulse Program or Erase

   – Internal timing generation

• CMOS and PCI I/O Compatibility

• Two Operational Modes

   – Low Pin Count (LPC) interface mode for in-system operation

   – Parallel Programming (PP) mode for fast production programming

• Low Pin Count (LPC) Interface Mode

   – LPC bus interface supporting byte Read and Write

   – 33 MHz clock frequency operation

   – WP# and TBL# pins provide hardware write protect for entire chip and/or top Boot Block

   – Block Locking Registers for individual block Write-Lock and Lock-Down protection

   – JEDEC Standard SDP Command Set

   – Data# Polling and Toggle Bit for End-of-Write detection

   – 5 GPI pins for system design flexibility

   – 4 ID pins for multi-chip selection

• Parallel Programming (PP) Mode

   – 11-pin multiplexed address and 8-pin data I/O interface

   – Supports fast In-System or PROM programming for manufacturing

• Packages Available

   – 32-lead PLCC

   – 32-lead TSOP (8mm x 14mm)

• All non-Pb (lead-free) devices are RoHS compliant