1. General Overview & Key Features

️· Memory Type: 1.8V Uniform Sector Flash Memory
️· Quad Mode: Supports quad I/O for faster data transfer. (Requires QE bit to be set, which is factory set and cannot be changed)

2. Quad I/O (QE Bit)

️· QE Bit Function: Enables/disables Quad I/O.
️· Initial State: QE = 1 (Quad I/O is enabled by default and *cannot* be changed). This means IO2 and IO3 are always used.

3. Status Register (Key Bits and Functions)

️· WIP (Write In Progress): Indicates if the memory is busy with a write/erase/status register operation.
- `WIP = 1`: Busy.
- `WIP = 0`: Idle.
️· WEL (Write Enable Latch): Controls write access.
- `WEL = 1`: Write enabled.
- `WEL = 0`: Write disabled.
️· BP4-BP0 (Block Protect): Non-volatile bits defining the size of a protected area. When set, prevent Program/Erase commands from affecting that area. Used in conjunction with CMP.
️· SRP1, SRP0 (Status Register Protect): Control how the Status Register can be written:
- (0, 0): Software Protected (Default - writable after WEL=1).
- (1, 0): Power Supply Lock-Down (Reset on power cycle)
- (1, 1): One-Time Programmable (Permanent lock after programming – *special order only*).
️· CMP (Compare): Used with BP4-BP0 to configure memory protection. Default: CMP=0.
️· SUS1, SUS2 (Suspend): Indicate if an Erase or Program Suspend operation is active. Set by Erase/Program Suspend (75H) and cleared by Resume (7AH), Reset or Power Cycle.
️· EN4B: Enable 4-byte mode. Default: 0.
️· LB2, LB3: OTP bits related to security registers.

4. Block Protection (BP4-BP0 and CMP)

️· The BP4-BP0 bits, when combined with the CMP bit, determine the protected memory area. (Refer to the provided tables in the document for specifics on how these bits interact to define the protected region)

5. Security Registers

️· Access to security registers is controlled by LB2 and LB3 bits in Status Register. By default, the security registers are unlocked (LB2=0, LB3=0).
️· Once LB2 and LB3 are programmed (OTP), the Security Registers become read-only.

Important Notes from the Document

️· Quad Mode is Permanent: The QE bit cannot be changed.
️· SRP1, SRP0 = (1,1) requires special order
️· The document references specific command codes (75H, 7AH, 66H+99H) for Suspend, Resume, and Reset operations. These are vital for controlling erase/program operations.
️· Refer to the provided tables for detailed information on how BP4-BP0 and CMP interact.