# Technical Overview of M95640-R EEPROM The **M95640-R** is a low-voltage, high-performance **64-Kbit Serial SPI EEPROM** (Electrically Erasable Programmable Memory) manufactured by STMicroelectronics. It is commonly used for parameter storage in automotive, industrial, and consumer electronics. --- ### 1. Key Technical Specifications | Parameter | Specification | | :--- | :--- | | **Memory Size** | 64 Kbits (8,192 bytes x 8 bits) | | **Interface** | SPI (Serial Peripheral Interface) | | **Operating Voltage (Vcc)** | 1.8V to 5.5V | | **Clock Frequency** | Up to 20 MHz (at 4.5V - 5.5V) | | **Page Size** | 32 Bytes | | **Endurance** | 4 million write cycles | | **Data Retention** | 200 years | | **Operating Temperature** | -40°C to +85°C (Standard) | --- ### 2. Pin Configuration and Functions The device is typically available in SO8, TSSOP8, or UFDFPN8 packages. The pinout is standard for SPI EEPROMs: | Pin | Name | Description | | :--- | :--- | :--- | | **1** | **S# (CS)** | Chip Select (Active Low) - Initiates communication. | | **2** | **Q (SO)** | Serial Data Output. | | **3** | **W#** | Write Protect - Hardware protection for memory. | | **4** | **Vss** | Ground. | | **5** | **D (SI)** | Serial Data Input. | | **6** | **C (SCK)** | Serial Clock - Synchronizes data transfer. | | **7** | **HOLD#** | Pause communication without resetting the Chip Select. | | **8** | **Vcc** | Supply Voltage. | --- ### 3. Core Electronic Features #### A. The SPI Protocol The M95640-R operates as a slave device. It supports SPI modes (0,0) and (1,1). Data is latched on the rising edge of the clock (`SCK`) and shifted out on the falling edge. #### B. Write Protection Mechanism The chip includes two layers of protection: 1. **Software Protection:** A Status Register containing **Block Protect bits (BP0, BP1)** allows the user to protect quarters, halves, or the entire memory array. 2. **Hardware Protection:** The `W#` pin, when pulled low, prevents changes to the Status Register (and thus the protected blocks) if the SRWD (Status Register Write Disable) bit is set. #### C. Page Write Buffer The device features a **32-byte page buffer**. This allows you to write up to 32 bytes in a single write cycle (taking approx. 5ms), which is significantly faster than writing byte-by-byte. --- ### 4. Implementation Example (Pseudo-Code) To communicate with the M95640-R using a microcontroller, you must send specific instruction opcodes. ```c // Common Instruction Opcodes #define WREN 0x06 // Write Enable #define WRITE 0x02 // Write to Memory Array #define READ 0x03 // Read from Memory Array #define RDSR 0x05 // Read Status Register /* Example: Writing 0xAA to address 0x0010 */ CS_Low(); SPI_Transfer(WREN); // Enable writing CS_High(); Delay(); CS_Low(); SPI_Transfer(WRITE); // Write command SPI_Transfer(0x00); // Address High Byte SPI_Transfer(0x10); // Address Low Byte SPI_Transfer(0xAA); // Data Byte CS_High(); ```