ST72F324J datasheet(137/156 Pages) STMICROELECTRONICS

137 / 156 page

ST72324J/K

137/156

12.9 CONTROL PIN CHARACTERISTICS

12.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.

Figure 88. Typical Application with RESET pin 6)7)8)

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

the RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-

vironments.

6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 12.9.1 . Otherwise the reset will not be taken into account internally.

8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value

specified for IINJ(RESET) in Section 12.2.2 on page 113.

9. Data guaranteed by design, not tested in production.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage 1)

0.16xVDD

VIH

Input high level voltage 1)

0.85xVDD

Vhys

Schmitt trigger voltage hysteresis 2)

2.5

VOL

Output low level voltage 3)

VDD=5V

IIO=+5mA

0.5

1.2

IIO=+2mA

0.2

0.5

IIO

Input current on RESET pin

TBD

RON

Weak pull-up equivalent resistor

120

Ω

tw(RSTL)out Generated reset pulse duration

External pin

429)

µs

Internal reset sources

429)

µs

th(RSTL)in External reset pulse hold time

2.5

µs

tg(RSTL)in Filtered glitch duration

200

0.01

µF

VDD

0.01

µF

EXTERNAL

RESET

CIRCUIT 5)

USER

VDD

4.7k

Ω

Required if LVD is disabled

Recommended

if LVD is disabled

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

LVD RESET

INTERNAL

RESET

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