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ST72324BL bảng dữ liệu(PDF) 119 Page - STMicroelectronics |
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ST72324BL bảng dữ liệu(HTML) 119 Page - STMicroelectronics |
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119 / 151 page  ST72F324L, ST72324BL 119/151 CLOCK CHARACTERISTICS (Cont’d) 12.5.5 PLL Characteristics Note: 1. Instantaneous PLL jitter is the absolute maximum deviation on a single clock period. Data characterized, not tested in production. Figure 63. PLL Clock Jitter vs. Application Signal frequency1 PLL clock jitter may cause application errors if high frequency signals are input or output by the appli- cation (e.g. high speed serial I/O or sampling of high frequency signals). Using the PLL increases clock jitter, however this is a periodic effect which is absorbed over several CPU cycles. The lower the frequency of the appli- cation signal, the less the impact. Figure 63 shows the effect of jitter (with and with- out PLL) on application signals in the range 125kHz to 2MHz. At frequencies of less than 125kHz, the jitter is negligible. Note 1: Measurement conditions: fCPU = 4MHz, TA= 25°C Symbol Parameter Conditions Min Typ Max Unit VDD(PLL) PLL Operating Range 2.85 3.6 V fOSC PLL input frequency range 2 4 MHz ∆ f CPU/fCPU Instantaneous PLL jitter 1) fOSC = 4 MHz. (fCPU=8MHz.) 3.5 5.5 % 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 2000 1000 500 250 125 Application Signal Frequency (KHz) FLASH DEVICES ROM DEVICES 1 |
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