ADAU1772BCPZ-R7 datasheet(106/117 Pages) AD

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Data Sheet

ADAU1772

Rev. C | Page 105 of 116

DECIMATOR POWER CONTROL REGISTER

Address: 0x0044, Reset: 0x00, Name: DECIM_PWR_MODES

These bits enable clocks to the digital filters and ASRC decimator filters of the ADCs. These bits must be enabled for all channels that will be used

in the design. To use the ADCs, these SINC_x_EN bits must be enabled along with the appropriate ADC_x_EN bits in the ADC_CONTROL2

and ADC_CONTROL3 registers. If the digital microphone inputs are used, the SINC_x_EN bits can be set without setting ADC_x_EN.

Table 95. Bit Descriptions for DECIM_PWR_MODES

Bits

Bit Name

Settings

Description

Reset

Access

DEC_3_EN

Control power to the ASRC3 decimator.

0x0

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DEC_2_EN

Control power to the ASRC2 decimator.

0x0

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DEC_1_EN

Control power to the ASRC1 decimator.

0x0

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DEC_0_EN

Control power to the ASRC0 decimator.

0x0

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SINC_3_EN

ADC3 filter power control.

0x0

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SINC_2_EN

ADC2 filter power control.

0x0

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SINC_1_EN

ADC1 filter power control.

0x0

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SINC_0_EN

ADC0 filter power control.

0x0

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