WM8321 datasheet(123/253 Pages) CIRRUS

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Production Data

WM8321

PD, February 2012, Rev 4.0

123

23.2.2 THERMAL INTERRUPTS

The primary TEMP_INT interrupt comprises a single secondary interrupt as described in Section 26.

The secondary interrupt bit is defined in Table 66.

The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event

is masked and does not trigger a TEMP_INT interrupt. The secondary interrupt bit in R16401 (4011h)

is valid regardless of whether the mask bit is set. The secondary interrupt is masked by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401 (4011h)

Interrupt Status

TEMP_THW_CINT

Thermal Warning interrupt

(Rising and Falling Edge triggered)

Note: Cleared when a ‘1’ is written.

R16410 (4019h)

Interrupt Status

1 Mask

IM_TEMP_THW_CINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 66 Thermal Interrupts

23.2.3 GPIO INTERRUPTS

The primary GP_INT interrupt comprises sixteen secondary interrupts as described in Section 21.4.

The secondary interrupt bits are defined in Table 67.

Each of the secondary interrupts can be masked. When a mask bit is set, the corresponding interrupt

event is masked and does not trigger a GP_INT interrupt. The secondary interrupt bits in R16405

(4015h) are valid regardless of whether the mask bit is set. The secondary interrupts are all masked

by default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16405 (4015h)

Interrupt Status

15:0

GPn_EINT

GPIO interrupt.

(Trigger is controlled by

GPn_INT_MODE)

Note: Cleared when a ‘1’ is written.

R16413

(401Dh)

Interrupt Status

5 Mask

15:0

IM_GPn_EINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Note: n

is a number between 1 and 12 that identifies the individual GPIO.

Table 67 GPIO Interrupts

23.2.4 ON PIN INTERRUPTS

The primary ON_PIN_INT interrupt comprises a single secondary interrupt as described in

Section 11.6. The secondary interrupt bit is defined in Table 68.

The secondary interrupt can be masked. When the mask bit is set, the corresponding interrupt event

is masked and does not trigger an ON_PIN_INT interrupt. The secondary interrupt bit in R16401

(4011h) is valid regardless of whether the mask bit is set. The secondary interrupt is masked by

default.

ADDRESS

BIT

LABEL

DESCRIPTION

R16401 (4011h)

Interrupt Status

ON_PIN_CINT

ON pin interrupt.

(Rising and Falling Edge triggered)

Note: Cleared when a ‘1’ is written.

R16409 (4019h)

Interrupt Status

1 Mask

IM_ON_PIN_CINT

Interrupt mask.

0 = Do not mask interrupt.

1 = Mask interrupt.

Default value is 1 (masked)

Table 68 ON Pin Interrupt

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