ST72561AR7-Auto datasheet(320/324 Pages) STMICROELECTRONICS

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Important notes

ST72561-Auto

320/324

Doc ID 12370 Rev 8

24.2

Flash/FastROM devices only

24.2.1

LINSCI wrong break duration

SCI mode

A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.

In some cases, the break character may have a longer duration than expected:

●

20 bits instead of 10 bits if M = 0

●

22 bits instead of 11 bits if M = 1

In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.

This may lead to generate one break more than expected.

Occurrence

The occurrence of the problem is random and proportional to the baud rate. With a transmit

frequency of 19200 baud (fCPU = 8 MHz and SCIBRR = 0xC9), the wrong break duration

occurrence is around 1%.

Workaround

If this wrong duration is not compliant with the communication protocol in the application,

software can request that an Idle line be generated before the break character. In this case,

the break duration is always correct assuming the application is not doing anything between

the idle and the break. This can be ensured by temporarily disabling interrupts.

The exact sequence is:

●

Disable interrupts

●

Reset and set TE (IDLE request)

●

Set and reset SBK (Break Request)

●

Re-enable interrupts

LIN mode

If the LINE bit in the SCICR3 is set and the M bit in the SCICR1 register is reset, the LINSCI

is in LIN master mode. A single break character is sent by setting and resetting the SBK bit

in the SCICR2 register. In some cases, the break character may have a longer duration than

expected:

●

24 bits instead of 13 bits

Occurrence

The occurrence of the problem is random and proportional to the baud rate. With a transmit

frequency of 19200 baud (fCPU = 8 MHz and SCIBRR = 0xC9), the wrong break duration

occurrence is around 1%.

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